IDT72255LA IDT [Integrated Device Technology], IDT72255LA Datasheet - Page 4

• Manufacturer Part Number: IDT72255LA
• Description: CMOS SUPERSYNC FIFO
• Manufacturer: IDT [Integrated Device Technology]

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18
PIN DESCRIPTION
Symbol
D
MRS
PRS
RT
FWFT/SI
WCLK
WEN
RCLK
REN
OE
SEN
LD
DC
FF
EF
PAF
PAE
Q
V
GND
HF
CC
0
0
/
–D
/
–Q
IR
OR
17
17
Data Inputs
Master Reset
Partial Reset
Retransmit
First Word Fall
Through/Serial In
Write Clock
Write Enable
Read Clock
Read Enable
Output Enable
Serial Enable
Load
Don't Care
Full Flag/
Input Ready
Empty Flag/
Output Ready
Programmable
Almost-Full Flag
Programmable
Almost-Empty Flag
Half-Full Flag
Data Outputs
Power
Ground
Name
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
Data inputs for a 18-bit bus.
MRS
all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT
Standard mode, one of two programmable flag default settings, and serial or
parallel programming of the offset settings.
PRS
all zeroes. During Partial Reset, the existing mode (IDT or FWFT), programming
method (serial or parallel), and programmable flag settings are all retained.
RT
the
the write pointer, programming method, existing timing mode or programmable flag
settings.
During Master Reset, selects First Word Fall Through or IDT Standard mode.
After Master Reset, this pin functions as a serial input for loading offset registers
When enabled by
offsets into the programmable registers for parallel programming, and when
enabled by
programmable register for serial programming.
WEN
When enabled by
memory and offsets from the programmable registers.
REN
SEN
During Master Reset,
1,023) and determines the flag offset programming method, serial or parallel. After
Master Reset, this pin enables writing to and reading from the offset registers.
This pin must be tied to either V
Reset.
In the IDT Standard mode, the
not the FIFO memory is full. In the FWFT mode, the
indicates whether or not there is space available for writing to the FIFO memory.
In the IDT Standard mode, the
not the FIFO memory is empty. In FWFT mode, the
OR
PAF
total word capacity of the FIFO minus the full offset value m, which is stored in the
Full Offset register. There are two possible default values for m: 127 or 1,023.
PAE
which is stored in the Empty Offset register. There are two possible default values
for n: 127 or 1,023. Other values for n can be programmed into the device.
HF
Data outputs for an 18-bit bus.
+5 Volt power supply pins.
Ground pins.
OE
asserted on the rising edge of RCLK initializes the READ pointer to zero, sets
indicates whether the FIFO memory is more or less than half-full.
EF
indicates whether or not there is valid data available at the outputs.
controls the output impedance of Q
initializes the read and write pointers to zero and sets the output register to
goes LOW if the number of words in the FIFO memory is more than
goes LOW if the number of words in the FIFO memory is less than offset n,
enables RCLK for reading data from the FIFO memory and offset registers.
enables serial loading of programmable flag offsets.
initializes the read and write pointers to zero and sets the output register to
enables WCLK for writing data into the FIFO memory and offset registers.
flag to LOW (
RT
SEN
is useful to reread data from the first physical location of the FIFO.
, the rising edge of WCLK writes one bit of data into the
WEN
REN
OR
LD
, the rising edge of RCLK reads data from the FIFO
to HIGH in FWFT mode) temporarily and does not disturb
, the rising edge of WCLK writes data into the FIFO and
selects one of two partial flag default offsets (127 or
Description
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
EF
FF
CC
function is selected.
function is selected.
or GND and must not toggle after Master
n.
IR
OR
function is selected.
FF
EF
function is selected.
indicates whether or
indicates whether or
IR
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