IDT72255LA IDT [Integrated Device Technology], IDT72255LA Datasheet - Page 23

• Manufacturer Part Number: IDT72255LA
• Description: CMOS SUPERSYNC FIFO
• Manufacturer: IDT [Integrated Device Technology]

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 8,192 for the IDT72255LA and 16,384 for the IDT72265LA.
2. For FWFT mode: D = maximum FIFO depth. D = 8,193 for the IDT72255LA and 16,385 for the IDT72265LA.
NOTES:
1. n =
2. For IDT Standard mode
3. For FWFT mode.
4. t
5.
WCLK
WCLK
RCLK
RCLK
time between the rising edge of WCLK and the rising edge of RCLK is less than t
PAE
SKEW2
PAE
is asserted and updated on the rising edge of WCLK only.
t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
CLKH
offset.
t
ENS
n words in FIFO
n+1 words in FIFO
Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
t
CLKL
t
[
ENH
(2) ,
t
SKEW2
1
(3)
D/2 words in FIFO
Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)
+ 1
(4)
]
words in FIFO
t
t
PAE
CLKH
(1)
2
,
(2)
t
ENS
t
CLKL
SKEW2
t
t
ENH
ENS
t
HF
, then the
n+1 words in FIFO
n+2 words in FIFO
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
t
ENS
PAE
[
D/2 + 1 words in FIFO
t
ENH
PAE
deassertion may be delayed one extra RCLK cycle.
+ 2
will go HIGH (after one RCLK cycle plus t
]
(2) ,
(3)
words in FIFO
t
HF
1
(1)
,
(2)
t
PAE
[
D/2 words in FIFO
2
+ 1
]
words in FIFO
n words in FIFO
n+1 words in FIFO
4670 drw 21
PAE
4670 drw 20
(1)
). If the
,
23
(2)
(2) ,
(3)