IDT72255LA IDT [Integrated Device Technology], IDT72255LA Datasheet - Page 25

• Manufacturer Part Number: IDT72255LA
• Description: CMOS SUPERSYNC FIFO
• Manufacturer: IDT [Integrated Device Technology]

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18
between WCLK and transfer clock, or RCLK and transfer
clock, for the
written to an empty depth expansion configuration. There will
be no delay evident for subsequent words written to the
configuration.
expansion configuration will "bubble up" from the last FIFO to
the previous one until it finally moves into the first FIFO of the
chain. Each time a free location is created in one FIFO of the
chain, that FIFO's
FIFO to write a word to fill it.
takes for
The "ripple down" delay is only noticeable for the first word
The first free location created by reading from a full depth
For a full expansion configuration, the amount of time it
FWFT/SI
WRITE ENABLE
INPUT READY
DATA IN
WRITE CLOCK
IR
of the first FIFO in the chain to go LOW after a word
OR
n
flag.
IR
line goes LOW, enabling the preceding
Dn
WCLK
Figure 20. Block Diagram of 16,384 x 18 and 32,768 x 18 Depth Expansion
FWFT/SI
72255LA
72265LA
IDT
•
TRANSFER CLOCK
RCLK
Qn
•
GND
n
has been read from the last FIFO is the sum of the delays for
each individual FIFO:
where N is the number of FIFOs in the expansion and T
is the WCLK period. Note that extra cycles should be added
for the possibility that the t
between RCLK and transfer clock, or WCLK and transfer
clock, for the
RCLK, whichever is faster. Both these actions result in data
moving, as quickly as possible, to the end of the chain and free
locations to the beginning of the chain.
The Transfer Clock line should be tied to either WCLK or
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
WCLK
IR
Dn
(N – 1)*(3*transfer clock) + 2 T
flag.
FWFT/SI
72255LA
72265LA
IDT
SKEW1
RCLK
specification is not met
Qn
OUTPUT ENABLE
n
OUTPUT READY
READ ENABLE
WCLK
READ CLOCK
DATA OUT
4670 drw 23
25
WCLK