IDT72255LA IDT [Integrated Device Technology], IDT72255LA Datasheet - Page 9

• Manufacturer Part Number: IDT72255LA
• Description: CMOS SUPERSYNC FIFO
• Manufacturer: IDT [Integrated Device Technology]

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
17
17
0
0
0
X
1
1
1
12
12
72255LA – 8,192 x 18–BIT
X
0
1
1
1
0
1
3FFH if
3FFH if
07FH if
07FH if
EMPTY OFFSET REGISTER
FULL OFFSET REGISTER
DEFAULT VALUE
DEFAULT VALUE
X
1
0
1
1
0
1
is HIGH at Master Reset
is HIGH at Master Reset
is LOW at Master Reset,
is LOW at Master Reset,
Figure 4. Programmable Flag Offset Programming Sequence
Figure 3. Offset Register Location and Default Values
X
1
1
0
1
X
X
WCLK
X
X
X
X
0
0
17
17
RCLK
X
X
X
X
X
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
13
13
72265LA – 16,384 x 18–BIT
Parallel write to registers:
Empty Offset
Full Offset
Parallel read from registers:
Serial shift into registers:
26 bits for the 72255LA
28 bits for the 72265LA
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
No Operation
Write Memory
Read Memory
No Operation
Empty Offset
Full Offset
3FFH if
3FFH if
07FH if
07FH if
EMPTY OFFSET REGISTER
FULL OFFSET REGISTER
DEFAULT VALUE
DEFAULT VALUE
is LOW at Master Reset,
is HIGH at Master Reset
is LOW at Master Reset,
is HIGH at Master Reset
Selection
4670 drw 07
4670 drw 06
9
0
0