IDT72255LA IDT [Integrated Device Technology], IDT72255LA Datasheet - Page 8

• Manufacturer Part Number: IDT72255LA
• Description: CMOS SUPERSYNC FIFO
• Manufacturer: IDT [Integrated Device Technology]

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18
Figure 9, 10 and 12.
PROGRAMMING FLAG OFFSETS
The IDT72255LA/72265LA has internal registers for these
offsets. Default settings are stated in the footnotes of Table 1
and Table 2. Offset values can be programmed into the FIFO
in one of two ways; serial or parallel loading method. The
selection of the loading method is done using the
pin. During Master Reset, the state of the
whether serial or parallel flag offset programming is enabled.
A HIGH on
offset values and in addition, sets a default
of 3FFH (a threshold 1,023 words from the empty boundary),
and a default
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
TABLE II –– STATUS FLAGS FOR FWFT MODE
TABLE I –– STATUS FLAGS FOR IDT STANDARD MODE
Relevant timing diagrams for FWFT mode can be found in
Full and Empty Flag offset values are user programmable.
Number of
Words in
FIFO
Number of
Words in
FIFO
LD
(
1)
PAF
during Master Reset selects serial loading of
offset value of 3FFH (a threshold 1,023
4,097 to (8,192-(m+1))
4,098 to (8,193-(m+1))
(8,192-m)
(8,193-m)
(n+1) to 4,096
(n+2) to 4,097
72255LA
1 to n
72255LA
8,192
1 to n+1
8,193
(2)
0
0
to 8,192
to 8,191
LD
(1)
(1)
input determines
PAE
(2)
offset value
LD
(Load)
8,194 to (16,385-(m+1))
8,193 to (16,384-(m+1))
(16,384-m)
(16,385-m)
(n+2) to 8,193
(n+1) to 8,192
words from the full boundary). A LOW on
Reset selects parallel loading of offset values, and in addition,
sets a default
from the empty boundary), and a default
07FH (a threshold 127 words from the full boundary). See
Figure 3, Offset Register Location and Default Values .
possible to read the current offset values. It is only possible to
read offset values via parallel read.
quence , summarizes the control pins and sequence for both
serial and parallel programming modes. For a more detailed
description, see discussion that follows.
grammed) any time after Master Reset, regardless of whether
serial or parallel programming has been selected.
72265LA
1 to n+1
In addition to loading offset values into the FIFO, it also
Figure 4, Programmable Flag Offset Programming Se-
The offset registers may be programmed (and repro-
72265LA
16,385
1 to n
16,384
0
0
(2)
to 16,384
to 16,383
(1)
(1)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
PAE
(2)
offset value of 07FH (a threshold 127 words
H
H
H
H
H
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
PAF
LD
H
H
H
H
L
L
H
H
H
H
L
L
4670 drw 05
offset value of
during Master
H
H
H
H
H
H
L
L
L
L
L
L
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