SST49LF004B-33-4C-EI SST [Silicon Storage Technology, Inc], SST49LF004B-33-4C-EI Datasheet - Page 12

• Manufacturer Part Number: SST49LF004B-33-4C-EI
• Description: 4 Mbit LPC Firmware Flash
• Manufacturer: SST [Silicon Storage Technology, Inc]

Data Sheet
Firmware Memory Read Cycle
TABLE 4: F
©2003 Silicon Storage Technology, Inc.
FIGURE 4: F
1. Field contents are valid on the rising edge of the present clock cycle.
Clock
Cycle
3-9
LFRAME#
10
11
12
13
14
15
16
17
1
2
LAD[3:0]
LCLK
IRMWARE
MADDR
RSYNC
START
MSIZE
IDSEL
Name
TAR0
TAR1
TAR0
TAR1
Field
DATA
DATA
IRMWARE
M
EMORY
1101b
M
Start
Field Contents
0000 (READY)
EMORY
0000 (1 Byte)
0000 to 1111
1111 (float)
1111 (float)
LAD[3:0]
IDSEL
0000b
YYYY
ZZZZ
ZZZZ
R
1111
1101
1111
EAD
A[27:24]
R
EAD
C
1
YCLE
A[23:20]
C
YCLE
A[19:16]
F
IN then Float
Float then IN
Float then
IELD
Direction
OUT then
LAD[3:0]
W
OUT
OUT
OUT
Float
OUT
MADDR
A[15:12]
IN
IN
IN
IN
AVEFORM
D
EFINITIONS
A[11:8]
12
Comments
LFRAME# must be active (low) for the device to respond.
Only the last field latched before LFRAME# transitions high
will be recognized. The START field contents (1101b) indi-
cate a Firmware Memory Read cycle.
Indicates which SST49LF004B device should respond. If the
IDSEL (ID select) field matches the value of ID[3:0], the device
will respond to the LPC bus cycle.
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
The MSIZE field indicates how many bytes will be trans-
ferred during multi-byte operations. The SST49LF004B only
supports single-byte operation. MSIZE=0000b
In this clock cycle, the master (Intel ICH) has driven the bus
to all ‘1’s and then floats the bus, prior to the next clock
cycle. This is the first part of the bus “turnaround cycle.”
The SST49LF004B takes control of the bus during this
cycle.
During this clock cycle, the device generates a “ready sync”
(RSYNC) indicating that the device has received the input
data.
ZZZZ is the least-significant nibble of the data byte.
ZZZZ is the most-significant nibble of the data byte.
In this clock cycle, the SST49LF004B drives the bus to all
ones and then floats the bus prior to the next clock cycle.
This is the first part of the bus “turnaround cycle.”
The host resumes control of the bus during this cycle.
A[7:4]
A[3:0]
MSIZE
0000b
TAR0
1111b
4 Mbit LPC Firmware Flash
Tri-State
TAR1
RSYNC
0000b
D[3:0]
DATA
SST49LF004B
D[7:4]
S71232-02-000
1232 F03.0
TAR
T4.0 1232
12/03