SST49LF004B-33-4C-EI SST [Silicon Storage Technology, Inc], SST49LF004B-33-4C-EI Datasheet - Page 14

• Manufacturer Part Number: SST49LF004B-33-4C-EI
• Description: 4 Mbit LPC Firmware Flash
• Manufacturer: SST [Silicon Storage Technology, Inc]

Data Sheet
LPC Memory Read Cycle
TABLE 6: LPC M
©2003 Silicon Storage Technology, Inc.
FIGURE 6: LPC M
1. Field contents are valid on the rising edge of the present clock cycle.
Clock
Cycle
LFRAME#
3-10
11
12
13
14
15
16
17
LAD[3:0]
1
2
LCLK
CYCTYPE
START
ADDR
SYNC
Name
+ DIR
TAR0
TAR1
DATA
DATA
TAR0
TAR1
Field
EMORY
1 Clock 1 Clock
0000b
Start
EMORY
CYCTYPE
010Xb
DIR
Field Contents
+
R
1111 (float)
1111 (float)
EAD
LAD[3:0]
R
A[31:28] A[27:24]
YYYY
010X
ZZZZ
ZZZZ
0000
1111
0000
1111
EAD
C
YCLE
C
1
YCLE
F
A[23:20] A[19:16]
IELD
Load Address in 8 Clocks
W
then Float
then Float
Direction
then OUT
then OUT
LAD[3:0]
AVEFORM
Float
Float
OUT
OUT
OUT
D
IN
IN
IN
IN
IN
Address
EFINITIONS
A[15:12]
14
Comments
LFRAME# must be active (low) for the device to respond. Only
the last field latched before LFRAME# transitions high will be
recognized. The START field contents (0000b) indicate an LPC
Memory cycle.
Indicates the type of LPC Memory cycle. Bits 3:2 must be “01b” for
memory cycle. Bit 1 indicates the type of transfer “0” for Read. Bit 0 is
reserved.
bit address phase. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
In this clock cycle, the host drives the bus to all 1s and then
floats the bus. This is the first part of the bus “turnaround cycle.”
The SST49LF004B takes control of the bus during this cycle.
The SST49LF004B outputs the value 0000b indicating that it
has received data.
ZZZZ is the least-significant nibble of the data byte.
ZZZZ is the most-significant nibble of the data byte.
In this clock cycle, the host drives the bus to all 1s and then
floats the bus. This is the first part of the bus “turnaround cycle.”
The SST49LF004B takes control of the bus during this cycle.
Address Phase for Memory Cycle. LPC protocol supports a 32-
A[11:8]
A[7:4]
A[3:0]
1111b
TAR0
2 Clocks
4 Mbit LPC Firmware Flash
Tri-State
TAR1
1 Clock
0000b
Sync
Data Out 2 Clocks
D[3:0]
D[7:4]
Data
SST49LF004B
S71232-02-000
1232 F05.1
TAR
T6.0 1232
12/03