SST49LF004B-33-4C-EI SST [Silicon Storage Technology, Inc], SST49LF004B-33-4C-EI Datasheet - Page 13

• Manufacturer Part Number: SST49LF004B-33-4C-EI
• Description: 4 Mbit LPC Firmware Flash
• Manufacturer: SST [Silicon Storage Technology, Inc]

4 Mbit LPC Firmware Flash
SST49LF004B
Firmware Memory Write Cycle
TABLE 5: F
©2003 Silicon Storage Technology, Inc.
FIGURE 5: F
1. Field contents are valid on the rising edge of the present clock cycle.
Clock
Cycle
LFRAME#
3-9
10
11
12
13
14
15
16
17
LAD[3:0]
1
2
LCLK
IRMWARE
IRMWARE
MADDR
RSYNC
START
MSIZE
IDSEL
Name
Field
DATA
DATA
TAR0
TAR1
TAR0
TAR1
M
EMORY
1110b
M
Start
EMORY
Field Contents
IDSEL
0000b
0000 (1 Byte)
0000 to 1111
1111 (float)
1111 (float)
W
LAD[3:0]
RITE
YYYY
ZZZZ
1110
1111
0000
1111
ZZZZ
A[27:24]
W
RITE
C
A[23:20]
YCLE
1
C
YCLE
A[19:16]
OUT then Float
Float then OUT
IN then Float
Float then IN
W
Direction
MADDR
A[15:12]
LAD[3:0]
AVEFORM
OUT
IN
IN
IN
IN
IN
IN
A[11:8]
13
A[7:4]
Comments
LFRAME# must be active (low) for the device to
respond. Only the last field latched before LFRAME#
transitions high will be recognized. The START field
contents (1110b) indicate a Firmware Memory Write
cycle.
Indicates which SST49LF004B device should
respond. If the IDSEL (ID select) field matches the
value of ID[3:0], the device will respond to the mem-
ory cycle.
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
The MSIZE field indicates how many bytes will be
transferred during multi-byte operations. The device
only supports single-byte writes. MSIZE=0000b
ZZZZ is the least-significant nibble of the data byte.
ZZZZ is the most-significant nibble of the data byte.
In this clock cycle, the host drives the bus to all '1's and
then floats the bus prior to the next clock cycle. This is
the first part of the bus “turnaround cycle.”
The SST49LF004B takes control of the bus during this
cycle.
During this clock cycle, the device generates a “ready
sync” (RSYNC) indicating that the device has received
the input data.
In this clock cycle, the SST49LF004B drives the bus to
all '1's and then floats the bus prior to the next clock
cycle. This is the first part of the bus “turnaround
cycle.”
The host resumes control of the bus during this cycle.
A[3:0]
MSIZE
0000b
D[3:0]
DATA
D[7:4]
TAR0
1111b
Tri-State
TAR1
RSYNC
0000b
S71232-02-000
1232 F04.0
TAR
Data Sheet
T5.0 1232
12/03