SST49LF004B-33-4C-EI SST [Silicon Storage Technology, Inc], SST49LF004B-33-4C-EI Datasheet - Page 16

• Manufacturer Part Number: SST49LF004B-33-4C-EI
• Description: 4 Mbit LPC Firmware Flash
• Manufacturer: SST [Silicon Storage Technology, Inc]

Data Sheet
Abort Mechanism
If LFRAME# is driven low for one or more clock cycles after
the start of a bus cycle, the cycle will be terminated. The
host may drive LAD[3:0] with '1111b' (ABORT nibble) to
return the interface to ready mode. The ABORT only
affects the current bus cycle. For a multi-cycle command
sequence, such as the Erase or Program SDP commands,
ABORT doesn't interrupt the entire command sequence,
only the current bus cycle of the command sequence. The
host can re-send the bus cycle for the aborted command
and continue the SDP command sequence after the device
is ready again.
Response to Invalid Fields for Firmware
Memory Cycle
The SST49LF004B will not explicitly indicate that it has
received invalid field sequences. The response to specific
invalid fields or sequences is as follows:
ID mismatch: If the IDSEL field does not match ID[3:0],
the device will ignore the cycle. See Multiple Device Selec-
tion section for details.
Address out of range: The address sequence is 7
fields long (28 bits) for Firmware Memory bus cycles, but
only A
Address A
writes to the flash core (A
(A
Invalid MSIZE field: If the device receives an invalid
MSIZE field during a Firmware Memory Read or Write
cycle, the device will reset and no operation will be
attempted. The SST49LF004B will not generate any kind
of response in this situation. Invalid size fields for a Firm-
ware Memory cycle are any data other than 0000b.
Once valid START, IDSEL, and MSIZE fields are received,
the SST49LF004B will always complete the bus cycle.
However, if the device is busy performing a flash Erase or
Program operation, no new Write command (memory write
or register write) will be executed.
©2003 Silicon Storage Technology, Inc.
22
=0).
22
and A
22
has the special function of directing reads and
18
:A
0
will be decoded by SST49LF004B.
22
=1) or to the register space
16
Response to Invalid Fields for LPC
Memory Cycle
ID mismatch: ID information is included in the address bits
of every LPC Memory cycle. Address bits A
used to select the device with proper IDs. The
SST49LF004B will compare the ID bits in the address field
with ID[3:0]. If the ID bits in the address do not correspond
to the hardware ID pins the device will ignore the cycle. See
Multiple Device Selection section for details.
Address out of range: The address sequence is 8 fields
long (32 bits). Address bits A
the device with proper IDs. The SST49LF004B responds to
address range FFFF FFFFH to FF80 0000H and
000F FFFFH to 000E 0000H during LPC memory cycle
transfers. Address A
reads and writes to the flash core (A
space (A
Once valid START, CYCTYPE + DIR, and address range
(including ID bits) are received, the SST49LF004B will
always complete the bus cycle. However, if the device is
busy performing a flash Erase or Program operation, no
new internal Write command (memory Write or register
Write) will be executed. As long as the states of LAD[3:0]
and LFRAME# are known, the response of the
SST49LF004B to signals received during the LPC cycle
should be predictable.
22
=0).
4 Mbit LPC Firmware Flash
22
has the special function of directing
23
, A
21
:A
22
SST49LF004B
19
=1) or to the register
S71232-02-000
are used to select
23
, A
21
:A
19
12/03
are