msm62x42b Oki Semiconductor, msm62x42b Datasheet - Page 14

• Manufacturer Part Number: msm62x42b
• Description: Real Time Clock Ic With Built-in Crystal
• Manufacturer: Oki Semiconductor

MSM62X42B
c) IRQ FLAG (D
d) 30 sec. ADJ bit (30 sec. ADJUST)
CE REGISTER (Control E Register)
a) MASK (D
54
This status bit corresponds to "L" or "OPEN" of the STD.P output pin. When STD.P="L", then
this bit=1 and when STD.P=OPEN, then this bit=0.
This bit indicates that an interrupt has occurred to a microcomputer mainly. When D0 of
register C
from "0" to "1" according to the timing set by D
When D
the STD.P output) remains until "0" is written into this bit. When this bit is "1" and timing
for a new interrupt occurs, the new interrupt is ignored. When D
cycle output waveform mode), the "1" of this bit (the "L" of the STD.P output) keeps "1" until
either "0" is written to this bit, or this bit automatically returns after 7.8125ms. The using
examples for the alarm are shown in the item "Set STD.P at alarm mode of APPLICATION
NOTE".
This is a bit for 30-second adjustment. When "1" is written into this bit, the compensation for
30 seconds is performed. The duration for 125 s from the time written into this bit should
not be read from or written into registeres S
This bit for 125 s from the time written into this bit is kept in "1" and then it will automatically
return to "0". After "1" is written into this bit, the registeres S
operationed with confirmation of automatical return to "0" of this bit.
This bit controls the STD.P output. When this bit=1, then the STD.P output becomes open.
When this bit=0, then the STD.P output=output mode. The relationship between the MASK
bit and STD.P output is shown as follows.
• In the case of interrupt mode (ITRPT/STND bit="1")
• In the case of fixed cycle output waveform mode (ITRPT/STND bit="0")
1
(ITRPT/STND) of the register C
E
0
(MASK)=0, then the STD.P output changes from OPEN to "L" and this bit changes
)
IN TRT/STND BIT = "1"
MASK BIT
STD.P OUTPUT
2
) (Interrupt Request FLAG)
"0"
"1"
WRITE “0” INTO IRQ FLAG BIT
E
"0"
is 1 (interrupt mode), the "1" of this bit (the "L" of
1
~ W (addresses 0 ~ C).
3
"1"
(t
1
) and D
"INTERRUPT" DOES
NOT OCCUR BECAUSE
MASK BIT IS "1"
"INTERRUPT" TIMING
2
(t
OPEN
LOW LEVEL
0
) of the register C
0
~ W (addresses 0 ~ C) are
¡ Semiconductor
1
(ITRPT/STND)=0 (fixed
E
.