msm62x42b Oki Semiconductor, msm62x42b Datasheet - Page 15

• Manufacturer Part Number: msm62x42b
• Description: Real Time Clock Ic With Built-in Crystal
• Manufacturer: Oki Semiconductor

¡ Semiconductor
b) ITRPT/STND (D
c) t
This is a bit which gives the meaning for STD.P output. When this bit="1", the request for
interrupt is outputted at the STD.P output and when this bit="0", a fixed cycle waveform with
a low-level pulse width of 7.8125ms is present at the STD.P output. However, at this time,
the MASK bit must equal 0, while the period in either modes is determined by t
t
OUTPUT
• When ITRPT/STND bit="1", this bit determines the interrupt period. When ITRPT/
• The timing of the STD.P output designated by t
1
0
STD.P
IN TRT/STND BIT = "0"
(D
(D
MASK BIT
STND bit="0", this bit determines the period of fixed timing waveform. The periods are
shown in the table below.
occurs to a clock digit.
3
2
) of register C
), t
1
(D
2
WHEN ITRPT/STND
BIT is "1"
WHEN ITRPT/STND
BIT is "0"
t
0
0
1
1
) (time 0, 1)
1
1
STD.P OUTPUT
) (INTERRUPT/STANDARD PULSE)
E
"0"
.
t
0
1
0
1
0
The special counter is not included for t
"1"
(EXAMPLE) WHEN t
1/64 second
1 second
1 minute
1 hour
"0"
Period
PM12:00
"1"
OUTPUT DOES NOT OCCUR
AT LOW LEVEL BECAUSE
MASK BIT IS "1"
1
= 1, t
OUTPUT TIMING
AUTOMATIC RETURN
(When “0” is written to IRQ FLAG bit, at that time, STD.P
output becomes open without awaiting automatic return.)
0
= 1 and MASK = 0
Duty CYCLE of "L" level when
INRPT/STND bit is "0".
OPEN
LOW LEVEL
1
and t
PM1:00
1
2
1/2
1/128
1/7680
1/460800
and t
occurs at the moment that a carry
0
.
OPEN
LOW LEVEL
OPEN
LOW LEVEL
MSM62X42B
0
(D
2
) and
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