PLL202-01 PhaseLink (PLL), PLL202-01 Datasheet
PLL202-01
Related parts for PLL202-01
PLL202-01 Summary of contents
Page 1
... PCI Cycle to Cycle jitter: 250ps. 48Mhz SDRAM to SDRAM skew: 500ps. PCI to PCI skew: 500ps. 24_48Mhz CPU to CPU skew 250ps VDD3 SDRAM(0:11) CPU to PCI skew 4ns, typical 2ns SDRAMIN to SDRAM skew 4ns, SDRAM12 typical 3.5ns. PLL202-01 VDDL1 VDD1 VDD1 IOAPIC ...
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... SUPER I/O after input data latched during power-on. B Buffered reference clock output after input data latched during power-on. Buffer input pin: The signal provided to this input pin is buffered SDRAM outputs. 2.5V Buffered reference clock. This pin will be LOW when CPU_STOP is O low. PLL202-01 Description Rev 04/21/00 Page 2 ...
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... PLL202-01 SDRAM IOAPIC Running Running Low Low Running Running PCI 80 40.0 75 37.5 41.7 33.4 34.3 37.3 68 34.0 33.4 40.0 38.3 36.3 35.0 35.0 37.5 31.0 33.3 33.8 32.5 31.5 39.3 38.4 95 31.7 90 30.0 85 28.3 41.5 40.0 38.8 37 ...
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... FS1 ( see Frequency selection Table ) 0 FS0 ( see Frequency selection Table ) 0 Frequency selection control bit 1=Via I2C, 0=Via External jumper 0 I2C Selection ( see Frequency selection Table ) 0 0=Normal 1=Spread Spectrum enable, 0.25% Center Spread 0 0=Normal 1=Tristate Mode for all outputs PLL202- R Rev 04/21/00 Page 4 ...
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... CPU1 ( Active/Inactive ) 1 CPU_F (Active/Inactive) Default Description 1 Reserved 1 PCI_F ( Active/Inactive ) 1 Reserved 1 PCI4 ( Active/Inactive ) 1 PCI3 ( Active/Inactive ) 1 PCI2 ( Active/Inactive ) 1 PCI1 ( Active/Inactive ) 1 PCI0 ( Active/Inactive ) Default Description 1 Reserved X Inverted Power on latched FS0 value (Read only) 1 48MHz 1 24MHz 1 Reserved 1 SDRAM ( 8: Active/Inactive ) 1 SDRAM ( 4 Active/Inactive ) 1 SDRAM ( 0 Active/Inactive ) PLL202-01 Rev 04/21/00 Page 5 ...
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... Default Description 1 Reserved 1 Reserved 1 Reserved 1 IOAPIC ( Active/Inactive ) 1 Reserved 1 Reserved 1 REF1 ( Active/Inactive ) 1 REF0 ( Active/Inactive ) Default 0 Revision ID Bit 3* 0 Revision ID Bit 2* 0 Revision ID Bit 1* 0 Revision ID Bit 0* 0 Vendor ID Bit 3* 0 Vendor ID Bit 2* 1 Vendor ID Bit 1* 1 Vendor ID Bit 0* PLL202-01 Description Rev 04/21/00 Page 6 ...
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... Linear programming magnitude bit 2 0 Linear programming magnitude bit 1 0 Linear programming magnitude bit 0 (LSB) Default 0 Reserved 0 Device ID Bit 6* 0 Device ID Bit 5* 0 Device ID Bit 4* 0 Device ID Bit 3* 0 Device ID Bit 2* 0 Device ID Bit 1* 0 Device ID Bit 0* PLL202-01 Description Description Rev 04/21/00 Page 7 ...
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... Motherboard Clock Generator for 440BX Type with 133MHz FSB PROGRAMMING OF CPU FREQUENCY To simplify traditional loop counter setting, the PLL202-01 device incorporates SMART-BYTE ™ technology with a single byte programming via I2C to better optimize clock jitter and spread spectrum performance. Detail of PLL202-01's dual mode frequency programming method is described below: 1 ...
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... VIN = 0V; Inputs with I IL1 no pull-up resistors VIN = 0V; Inputs with I IL2 pull-up resistors R Pin 2,7,25,26,41, Pin 3. Logic Inputs IN C XIN & XOUT pins INX PLL202-01 MIN. MAX 0 0 0 -65 ...
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... CPU to CPU SDRAM to SDRAM PCI to PCI Measured @ 1.5V, equal loads CPU to SDRAM SDRAMIN to SDRAM CPU to PCI CPU_F,CPU1 V =3.3V(2.5V REF0,48MHz,24MHz, PCI_F,PCI V =3. SDRAM,SDRAM_F, REF1 IOAPIC V =3.3V(2.5V PLL202- MIN. TYP. MAX 250 250 500 250 ...
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... CPU_F,CPU1 V = 1.25V 2.5V 5%) DD IOAPIC CPU Measured @ 1.25V IOAPIC PCI Measured @ 1.5V REF,48MHz,24MHz CPU Measured @ 1.25V IOAPIC PCI Measured @ 1.5V REF,48MHz,24MHz Measured @ 1.25V CPU Measured @ 1.5V PCI PLL202- MIN. TYP. MAX 120 70 90 120 105 ...
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... MIN (0.20 - 0.41) 48PIN SSOP 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL202- PLL202-01 0.025 0.835 0.088 - 0.096 (2.250 - 2.450) 0.097 - 0.104 (2.467 - 2.642) TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE ...