PLL202-14 PhaseLink (PLL), PLL202-14 Datasheet

PLL202-14

Manufacturer Part Number

PLL202-14

Description

Ali, Via, Sis, Intel 440BX Chipset FTGS , Freq. Progr., Power Mgt, Wdt, Drive Ctrl, SST

Manufacturer

PhaseLink (PLL)

Datasheet

1.PLL202-14.pdf (14 pages)

Current page: 1 of 14
Download datasheet (197Kb)

FEATURES

BLOCK DIAGRAM

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

FS (0:4)*

SDATA

Generates all clock frequencies for

Pentium /

Support 3 CPU clocks, 3 AGP and 9 PCI.

Enhanced PCI Output Drive selectable by I2C.

One 48MHz clock (or 24_48MHz clock via I2C).

Three 2.5V APIC and two 14.318MHz ref. Clocks.

Power management control to stop CPU, PCI,

AGP, and APIC clocks.

Supports 2-wire I2C serial bus interface with

readback.

Single byte micro-step linear Frequency

Programming via I2C with glitch free smooth

switching.

Built-in programmable watchdog timer up to 63

seconds with 1-second interval. It will generate a

low reset output when timer expired.

Spread Spectrum 0.25% center, 0.5% center,

50% duty cycle with low jitter.

Available in 300 mil 48 pin SSOP.

XOUT

SCLK

0.75% center, and 0 to –0.5% downspread .

XIN

Logic

XTAL

PLL1

PLL2

OSC

SST

I2C

system processor.

Control

Logic

Watch

Programmable Clock Generator for VIA Apollo Pro-266

Dog

VDD1

REF(0:1)

VDDL2

CPU (0:2)

VDDL1

APIC (0:2)

VDD4

AGP (0:2)

VDD3

PCI (0:7)

PCI_F

VDD2

48Mhz

24_48Mhz

WDRESET#

PIN CONFIGURATION

Note: ^: Pull up #: Active low

POWER GROUP

KEY SPECIFICATIONS

: Bi-directional up latched at power-up

VDD1: REF(0:1), XIN, XOUT, PLL CORE

VDD2: 48MHz or 24_48MHz

VDD3: PCI(0:7), PCI_F

VDD4: AGP(0:2)

VDDL1: APIC(0:2)

VDDL2: CPU(0:2)

CPU Cycle to Cycle jitter: 250ps.

PCI Cycle to Cycle jitter: 500ps.

PCI to PCI skew: 500ps.

CPU to CPU skew 175ps.

CPU to PCI skew (CPU lead): typical 2ns.

AGP to AGP skew: 250ps.

24_48MHz/FS2

48MHz/FS3

XOUT

PCI_F

VDD2

VDD3

AGP0

VDD1

VDD3

FS1^

FS0^

GND

PCI0

PCI1

GND

PCI2

PCI3

PCI4

PCI5

PCI6

GND

PCI7

XIN

PLL202-14

Rev 3/23/01 Page 1

CPU0

REF0

REF1/FS4

VDDL1

APIC0

APIC1

GND

APIC2

VDDL2

GND

CPU1

VDDL2

GND

CPU2

CPU_STOP / WDRESET#

PCI_STOP

PD#

VDD4

GND

SDATA

SCLK

AGP2

AGP1

GND

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