PLL202-01 PhaseLink (PLL), PLL202-01 Datasheet - Page 8

• Manufacturer Part Number: PLL202-01
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , Freq. Progr., Power Mgt, SST
• Manufacturer: PhaseLink (PLL)

PROGRAMMING OF CPU FREQUENCY
To simplify traditional loop counter setting, the PLL202-01 device incorporates SMART-BYTE ™
technology with a single byte programming via I2C to better optimize clock jitter and spread spectrum
performance. Detail of PLL202-01's dual mode frequency programming method is described below:
1. ROM-table Frequency Programming:
2. Micro-step Linear Frequency Programming:
FREQUENCY PROGRAMMING EXAMPLE:
1. Procedures to program target CPU frequency to 139.0 Mhz:
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
The pre-defined 32 frequencies found in Frequency table can be accessed either through 5 external
jumpers or by setting internal I2C register in BYTE0.
CPU Frequency can be programmed via I2C in fine and linear positive or negative stepping around
selected CPU frequency in Frequency table. The highest step is either +127 or -127. Other bus
frequencies will be changed proportionally with the rate that CPU frequency change. The formula is
as follow:
A. Locate the closest CPU frequency from Frequency-ROM table: 135
B.
C. Solve M (Linear Magnitude factor) in integer:
D. Program I2C register:
= 0.22
Motherboard Clock Generator for 440BX Type with 133MHz FSB
F
F
FS3 FS2 FS1 FS0 CTR FS4
Sign M6
7
7
0 0 0 0 1 1 0 0
0 0 0 1 0 0 1 0
CPU
PCI
M = (F
6
6
= 135 + (0.22) * 18 = 138.96 ( % of frequency increased = 2.9 % )
= 33.8 * (1+2.9%) = 34.8
= (139 - 135) / 0.22
= 18
M5
5
5
Where:
CPU
M4
4
4
- F
M3
3
3
CPU
-
M2
1. M is magnitude factor defined in I2C Byte 7.bit(0:6)
2.
3.
2
2
ROMTABLE
M1
F
1
1
(sign bit) of M is defined in I2C Byte7.bit 7
is a constant
= 0.22
CPU
M0
0
0
) /
=
F
Setting of M = +18 in I2C.BYTE7
Setting of I2C.BYTE0
CPU.ROM-Table
(=0.22)
*
M
PLL202-01
Rev 04/21/00 Page 8