PLL202-01 PhaseLink (PLL), PLL202-01 Datasheet - Page 2

• Manufacturer Part Number: PLL202-01
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , Freq. Progr., Power Mgt, SST
• Manufacturer: PhaseLink (PLL)

PIN DESCRIPTIONS
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
REF0//PCI_STOP
PCI_F, PCI(0:4)
SDRAM (0:11),
CPU_F, CPU1
PCI_F/MODE
CPU_STOP
24MHz/F1*
48MHz/F0*
SDRAM_F
REF1/FS2
SDRAMIN
REF1/F2*
PCI0/F3*
SDATA
IOAPIC
VDDL1
VDDL2
48MHz
24MHz
Name
VDD1
VDD2
VDD3
VDD4
XOUT
SCLK
GND
XIN
Motherboard Clock Generator for 440BX Type with 133MHz FSB
38,37,35,34,32,
31,29,28,21,20,
7,8,10,11,12, 13
8,46,25,26
3,9,16,22,
Number
19,30,36
33,39,45
18,17,40
44,43
6,14
27
48
42
23
24
41
26
25
46
15
47
1
4
5
2
7
Type
O
O
O
O
O
P
P
P
P
P
P
P
B
B
B
B
B
B
B
I
I
I
I
Power supply for REF0, REF1, and crystal oscillator.
Power supply for PCI_F, PCI(0:4).
Power supply for SDRAM(0:11), SDRAM_F.
Power supply for 24MHz and 48MHz.
Power supply for IOAPIC (2.5V).
Power supply for CPU_F and CPU1 (2.5V).
Ground.
14.318MHz crystal input to be connected to one end of the crystal.
14.318MHz crystal output.
At power up, these pins are input pins and will determine the CPU clock
frequency. After input sampling, these pins will generate output clocks.
FS0, FS1 and FS2 have internal pull up (high by default) while FS3 has
internal pull down (low by default).
PCI clocks with frequencies defined by Frequency Table. These pins
except PCI_F will be LOW when PCI_STOP is LOW.
CPU clocks with frequencies defined by Frequency Table. These pins
are LOW when CPU_STOP is LOW except CPU_F.
Buffer output from SDRAMIN pin. These pins are LOW when CPU_STOP
is LOW except SDRAM_F is free running output.
Serial data input for serial interface port.
Multiplexed pin controlled by MODE signal. PCI_STOP will stop PCI
clock except PCI_F when LOW.
CPU_STOP input will stop CPU1, IOAPIC and SDRAM(0:11) when LOW.
At power-on, MODE function will be activated. When MODE is Low, Pin
2 is input for PCI_STOP. When high, Pin2 is output for REF0. After input
data latched, this pin will generate free running PCI bus clock.
48MHz output for USB after input data latched during power-on.
24MHz output for SUPER I/O after input data latched during power-on.
Buffered reference clock output after input data latched during power-on.
Buffer input pin: The signal provided to this input pin is buffered to 13
SDRAM outputs.
2.5V Buffered reference clock. This pin will be LOW when CPU_STOP is
low.
Description
PLL202-01
Rev 04/21/00 Page 2