PLL202-11D PhaseLink (PLL), PLL202-11D Datasheet - Page 4

• Manufacturer Part Number: PLL202-11D
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , Freq. Progr., Wdt, SST
• Manufacturer: PhaseLink (PLL)

I2C BUS CONFIGURATION SETTING
I2C CONTROL REGISTERS
1. BYTE 0: Functional and Frequency Select Clock Register (1=Enable, 0=Disable)
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Receiver/Transmitter
Address Assignment
Serial Bits Reading
Data Transfer Rate
Data Protocol
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Slave
Motherboard Clock Generator for 440BX Type with 133MHz FSB
Pin#
46
25
26
8
-
-
-
-
A6
Provides both slave write and readback functionality
Standard mode at 100kbits/s
The serial bits will be read or sent by the clock driver in the following order
Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N – Bits 7, 6, 5, 4, 3, 2, 1, 0
This serial protocol is designed to allow both blocks write and read from the controller. The
bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred
must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will
terminate the transfer. The write or read block both begins with the master sending a slave
address and a write condition (0xD2) or a read condition (0xD3).
Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte
Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte
Count Byte will be read by the master then all other Data Byte. Byte Count Byte default at
power-up is = (0x09).
1
A5
-
1
Default
0
0
0
0
0
0
1
0
A4
0
Description
FS3 ( see Frequency selection Table )
FS2 ( see Frequency selection Table )
FS1 ( see Frequency selection Table )
FS0 ( see Frequency selection Table )
Frequency selection control bit 1=Via I2C, 0=Via External jumper
I2C Selection ( see Frequency selection Table )
0=Normal 1=Spread Spectrum enable, 0.25% Center Spread
0=Normal 1=Tristate Mode for all outputs
A3
1
A2
0
A1
0
PLL202-11 rev. D
A0
1
R/W
_
Rev D 10/19/00 Page 4