PLL202-11D PhaseLink (PLL), PLL202-11D Datasheet - Page 9

• Manufacturer Part Number: PLL202-11D
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , Freq. Progr., Wdt, SST
• Manufacturer: PhaseLink (PLL)

BUILT-IN WATCHDOG TIMER (WDT)
Watchdog timer is used to perform safe recovery if frequency switching causes system to enter into
“Hang-up” state within a reasonable period of time (or Watchdog time interval). While disabled, the
watchdog time interval can be programmed between 0 and 32 seconds with increment of 0.5 second by
setting the value of I2C.Byte8.Bit(5:0). Once Enabled, WDT has to be disabled within a period that is
shorter than the programmed watchdog interval; otherwise WDT will generate a 500ms low watchdog
reset pulse to provoke a system reset. After system restarts, the PLL202-11 will start from predefined
Fall-back Frequency (the value of I2C Byte6,bits(7:3)). If system for any reason fails again at Fall-back
Frequency, the internal hardware will then generate a watchdog reset to restart the system from the
value of external hardware jumper setting to ensure a safe recovery.
Example usage:
1.
2A. Switch to target CPU=100.0MHz frequency with following I2C register setting:
2B. Switch to target CPU=78Mhz within the same timing Group
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
System power-up at CPU= 66.8MHz where external jumpers are used.
Motherboard Clock Generator for 440BX Type with 133MHz FSB
The fall-back frequency is set to the same location as that of FSEL since
frequency switching between different timing groups will cause system to hang
up. After WD timer expired or 7 seconds, the system will restart properly at target
100.0MHz if CPU is capable; otherwise WDT will perform another reset action to
restart the system from 66.8 Mhz
The fall-back frequency is recommended to set at the most safe and comfortable
level to ensure a successful reboot such as 70 or 75.3 if system is unable to
switch to 78Mhz.
FS3 FS2 FS1 FS0 CTR FS4
Sign M6
ENB
FB4 FB3 FB2 FB1 FB0
7
7
7
7
0 0 1 1 1 0 0 0
0 0 0 0 0 0 0 0
1 0 0 0 0 1 1 1
0 0 0 1 1 0 0 0
6
6
6
6
M5
T5
5
5
5
5
M4
T4
4
4
4
4
M3
T3
3
3
3
3
M2
T2
2
2
2
2
M1
T1
1
1
1
1
M0
T0
0
0
0
0
FSEL
M =0
WD-Timer = 7s
FBSEL
Setting in I2C.BYTE0
Setting in I2C.BYTE7
Setting in I2C.BYTE6
Setting in I2C.BYTE8
PLL202-11 rev. D
Rev D 10/19/00 Page 9