PLL202-13 PhaseLink (PLL), PLL202-13 Datasheet - Page 2

• Manufacturer Part Number: PLL202-13
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , Freq. Progr., SST
• Manufacturer: PhaseLink (PLL)

PIN DESCRIPTIONS
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
SDRAM (0:13)
CPU2.5_3.3*
48MHz/FS0*
WDRESET#
REF0/FS3*
24_48MHz/
PCI0/FS1*
PCI1/FS2*
CPU (0:2)
PCI (0:6)
SDATA
VDDL1
48MHz
Name
VDD0
VDD1
VDD2
VDD3
VDD4
XOUT
SCLK
REF0
GND
XIN
Motherboard Clock Generator for SIS540/630 with 133MHz FSB
17,18,20,21,28,
29,31,32,34,35,
7,8,9,11,12,
19,30,36,42
37,38,40,41
3,10,16,22,
Number
33,39,44
46,45,43
2,7,8,26
13,14
15
27
47
23
24
26
25
48
1
6
4
5
2
Type
O
O
O
O
O
O
O
P
P
P
P
P
P
P
B
B
B
I
I
Power supply for PLL Core.
Power supply for REF0, REF1, and crystal oscillator.
Power supply for PCI (0:6).
Power supply for SDRAM (0:13).
Power supply for 24_48MHz and 48MHz.
Power supply for CPU (0:2) 2.5V.
Ground.
14.318MHz crystal input to be connected to one end of the crystal.
14.318MHz crystal output.
At power up, these pins are input pins and will determine the CPU clock
frequency. After input sampling, these pins will generate output clocks.
They have internal pull down (low by default).
PCI clocks with frequencies defined by Frequency Table.
CPU clocks with frequencies defined by Frequency Table.
SDRAM clocks with frequencies defined by Frequency Table.
Serial data input for serial interface port.
48MHz output for USB after input data latched during power-up.
Clock output for SUPER I/O after input data latched during power-up. It
can be programmed by setting I2C byte1.bit7 to select either 24Mhz
(default) or 48Mhz. CPU2.5_3.3 input will program internal CPU skew
circuits based on CPU voltage. If high, it selects 2.5V. If Low, it selects
3.3V (default).
This pin is an open drain output. It will be Low at watchdog timer
expiration.
Buffered reference clock after input data latched during power-up.
Description
PLL202-13
Rev 02/15/00 Page 2