mx98743 Macronix International Co., mx98743 Datasheet - Page 14

• Manufacturer Part Number: mx98743
• Description: 100 Base Fast Ethernet Management Chip
• Manufacturer: Macronix International Co.

7.0 Programming Guide
7.1 GENERAL DESCRIPTION OF REGISTER ACCESS METHODS
7.2 SRAM ACCESS & FEM REGISTER SELECTION TABLE
RS12 RS11 RS[10:8] RS[7:1]
All the FEM registers, attributes as well as XRC registers can be accessed through the CPU interface
directly with indexing. All registers are 16-bit wide and mapped directly to RS[12:0] is used to determine
FEM Register selection or SRAM access. RS12=0 indicates FEM register select; RS12=1 indicates
SRAM access. For SRAM access, RS[11:0] is mapped to MA[11:0] for 4Kbyte memory; 0h-7ffh for receive
buffer, 800h-fffh for transmit buffer.
Each entry in the following tables represents a 16-bit wide register space. Only RS0 is used to selected the
bytes within the 16-bit register if the datapath is 8-bit wide; however, RS[12:2] are needed to access the
registers if 32-bit datapath is selected.
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
x
x
0
0
0
0
0
0
0
0
Table 6-1. SRAM Access & FEM Register Selection Table
0C
0A
0E
00
02
04
06
08
12
14
x
x
RS0
x
x
x
x
x
x
x
x
x
x
x
x
SRAM Access, 0-7ffh:Receive Buffer
SRAM Access, 800-fffh:Transmit Buffer
Repeater Interrupt Status Register
Repeater Interrupt Mask Register
Port Link/Partition Change Interrupt Status Register
Port Link/Partition Change Interrupt Mask Register
Data Rate Mismatch/Jabber Interrupt Status Register
Data Rate Mismatch/Jabber Interrupt Mask Register
Isolation/SA Change Interrupt Status Register
Isolation/SA Change Interrupt Mask Register
Sample Period Register
Sample Enable Register
14
REGISTER
MX98743
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
INDEX