mx98743 Macronix International Co., mx98743 Datasheet - Page 7

• Manufacturer Part Number: mx98743
• Description: 100 Base Fast Ethernet Management Chip
• Manufacturer: Macronix International Co.

PIN#
31
32
34
35
36
REGLCH
PTSCEN
XRCR/W
REGCK
NAME
IPDIS
I/O, TTL
O, TTL
I/O
I/O
I/O
O
Table 5-3. XRC Register Access Pins, 8 pins
Port Enable/Scramble Enable. If XRCR/W is high, each port's Enable/Scramble
status is displayed at the rising edge of REGCK and the serial input data is
stored in Register RS[12:1]=016h. If XRCRW is low, the content of Register
RS[12:1]=016h is read out serially.
Isolation/Partition Disable. If XRCR/W is high, each port's Isolation/Partition
status is displayed at the rising edge of REGCK and the serial input data is
stored in Register RS[12:1]=01Eh. If XRCRW is low, the content of Register
RS[12:1]=01Eh is read out serially.
XRC Read or Write. High indicates 'Read' Mode; register is being read out.
Low indicates 'Write' Mode. The FEM will issue XRC register write cycle when
the CPU is writing Register RS[12:1]=016h or 01Eh.
Register Latch. REGLCH is an input pin when XRCRW is held high and an
output pin when XRCRW is held low.
Register Clock . This pin is providing the 12.5MHz frequency whenever the FEM
is accessing the XRC registers.
7
DESCRIPTION
MX98743
INDEX