mx98743 Macronix International Co., mx98743 Datasheet - Page 5

• Manufacturer Part Number: mx98743
• Description: 100 Base Fast Ethernet Management Chip
• Manufacturer: Macronix International Co.

5.0 PIN DESCRIPTION
PIN#
9-12
141
142
1-4
15
14
8
6
7
TXD[3:0]
RXD3-0
RXCLK
TXCLK
NAME
RXDV
RXER
TXEN
CRS
COL
I, TTL
I, TTL
I. TTL
I, TTL
I, TTL
I, TTL
I, TTL
I/O
O
O
Table 5-1. Media Independent Interface, 15 pins
Receive Data Valid MII. Synchronous to RXCLK's rising edge. This signal
remains asserted through the whole frame, starting with the start-of-frame
delimiter and excluding any end-of-frame delimiter.
Carrier Sense MII. This pin, synchronous to RXCLK in TX mode, is asserted
when the receiving medium is not idle.
Receive Error. This pin is synchronous to RXCLK's rising edge. While RXDV
is asserted, i.e. a frame is being received, this signal is asserted if any coding
error is detected.
Receive Clock MII. 25 MHz continuous clock that provides the timing
reference for the transfer of the RXDV, RXD and RXER signals.
Receive Data MII. RXD3-0 are synchronous to RXCLK's rising edge with
RXD3 being the Most Significant Bit. For each RXCLK period in which RXDV
is asserted, RXD3-0 should be latched by the MAC. While RXDV is deasserted
, RXD3-0 are the 5B/4B nibbles decoded from RDAT4-0.
Collision Mll. This signal is asserted if both the receiving media and TXEN are
active.
25 MHz Transmit Clock Input.
Transmit Enable. This output becomes active when the first data packet is
valid on TXD3-0 and goes low after the last packet is clocked out of TXD[3:0].
Transmit Data MII. TXD3-0 are synchronous to TXCLK's rising edge with
TXD3 being the Most Significant Bit
5
DESCRIPTION
MX98743
INDEX