mx98743 Macronix International Co., mx98743 Datasheet - Page 8

• Manufacturer Part Number: mx98743
• Description: 100 Base Fast Ethernet Management Chip
• Manufacturer: Macronix International Co.

64-67, 69,
70, 73, 74,
76-79,
82-85,
87-90,
93-95,
98-101,
103-106
40-39,
41-44,
46-50,
52-55
PIN#
56
58
59
60
CPUD0-31
DWS[1:0]
RS12-0
NAME
RDY
R/W
INT
CS
O,OD
O,OD
I,TTL
I,TTL
I,TTL
I,TTL
I/O
I/O
Chip Select. This pin, active low, is used to access the FEM internal
register or SRAM buffer when held low.
System Read/Write. High for read, and low for write.
Ready. This pin, active low, is an tri-state output.
Interrupt. Active low. Open Drain.
Data. A group of 8,16, or 32 pins can become active depending on the
value of DWS1-0. Inactive pins are tri-stated.
Datapath Width Selection. These two pins determin which datapath
FEM Register or CPU Selection. When RS12=0, RS[11:0] represents
FEM internal registers select pins. When RS12=1, RS[11:0]
represents CPU interface address lines. RS[11:0] is mapped to
MA[11:0] for 4Kbytes memory: 0h~7ffh for receive buffer, and
800h~fffh for transmit buffer.
width for CPUD31-0.
Table 5-4. CPU Interface, 51 pins
DWS[1:0] = '00' :
8
= '01' or '10' : 16 bit,
= '11' :
DESCRIPTION
32 bit.
8 bit,
MX98743
INDEX