ch5001a ETC-unknow, ch5001a Datasheet - Page 14

• Manufacturer Part Number: ch5001a
• Description: Cmos Color Digital Video Camera
• Manufacturer: ETC-unknow

that, the master may read another data byte and so on. In summary, a RESTART condition, followed by a DAB,
must be produced by the master before each of the RAB and before each of the data read events. Two consecutive
alternating read cycles are shown in Figure 9.
If AutoInc = 1, then the address register will be incremented automatically and subsequent data bytes can be read
from successive registers, without providing a second RAB
When the auto-increment mode is enabled (AutoInc is set to 1), the address register will continue incrementing for
each read cycle. When the content of the Address Register reaches 2A, it will wrap around and start from 00h again.
The auto increment sequence can be terminated by either a STOP or RESTART condition. The read operation can
be terminated with a “STOP” condition.
RESTART condition. The CH5001 contains 38 control registers each with a maximum of 8 usable bits to provide
access to basic video attribute control functions. These registers are accessible via the 2-bit serial bus (SD & SC).
The following sections describe the functions and the controls available through these registers.
CHRONTEL
14
SC
SD
SD
SC
Condition
Condition
Start
Start
Device ID
Device
1 - 7
1 - 7
Device
1 - 7
R/W*
I
8
2
acknowledge
R/W*
C
R/W*
CH5001
I
8
2
acknowledge
C
8
acknowledge
ACK
CH5001
CH5001
9
ACK
ACK
9
9
Figure 10: Auto-increment Read Cycle
RAB n
1 - 8
Figure 9: Alternating Read Cycle
RAB 2
1 - 8
RAB 1
1 - 8
CH5001
Figure 10 shows an auto-increment read cycle terminated by a STOP or
ACK
acknowledge
9
acknowledge
CH5001
CH5001
ACK
Condition
ACK
9
Restart
9
10
Condition
Condition
Restart
Restart
10
Device
10
1 - 7
Device ID
Device
1 - 7
R/W*
1 - 7
I
8
2
C
acknowledge
CH5001
ACK
R/W*
R/W*
9
I
8
2
C
I
8
2
C
acknowledge
acknowledge
Data n
CH5001
ACK
1 - 8
CH5001
ACK
9
9
acknowledge
Master
ACK
Data 2
1 - 8
9
Data 1
201-0000-032 Rev 3.0, 6/2/99
1 - 8
Master does
not acknowledge
Data
1 - 8
n+1
acknowledge
Master does
not acknowledge
just before Stop
condition
ACK
does not
ACK
9
Master
9
ACK
CH5001A
Condition
9
Condition
Restart
Stop
10
Condition
Stop