ch5001a ETC-unknow, ch5001a Datasheet - Page 30

• Manufacturer Part Number: ch5001a
• Description: Cmos Color Digital Video Camera
• Manufacturer: ETC-unknow

CHRONTEL
Miscellaneous Register 2
Bit 0 (Master Clock Frequency) of register MISC2 refers to the CH5001 the master clock (XO) frequency. A 0
should be written to this location when the master clock is 24MHz. A 1 should be written to this location when the
master clock is 27MHz. When modes four or five are selected (M[2:0] =4,5), the master clock must be 27MHz.
Bit 1 (Data Valid Control) of register MISC2 selects whether or not the CLKOUT signal is gated. When this bit is a
0, the CLKOUT pin will produce a continuous clock output signal. When bit DVC is a 1, the CLKOUT will be
gated, and will be active when active data is being output from the CH5001, and inactive when non-active data is
present at the outputs.
Bit 2 (CLKOUT Polarity) of register MISC2 selects the polarity of the CLKOUT signal. A 0 in this location means
output data has been latched with the positive edge of the CLKOUT signal. A 1 in this location means output data
has been latched with the negative edge of the CLKOUT signal.
Bit 3 (A/D Direct Output) of register MISC2 selects whether the output signal is directly from the A/D converter or
after the datapath postprocessing. In both cases, the relationship between the Hsync, Vsync and active video will
remain the same. When a 1 is written to this location, the Y[7:0] and C[7:0] will output luma and chroma data from
the datapath circuitry. When a 0 is written to this location, the Y[7:0] pins will contain the A/D data directly. With
no postprocessing and the C[7:0] outputs will be set to 128. If 8-bit output mode is selected, the A/D output will be
multiplexed with the decimal value 128 to enable connection to an 8-bit video encoder resulting in a black and white
image.
Bits 4-6 of Register MISC2 are reserved.
Bit 7 (Refresh Enable) enables memory refresh.
Miscellaneous Register 3
Bits 0-3 (Clock Delay) of register MISC3 determine the clock delay between internal clock signals. The
recommended value is 9.
Bit 7 (A/D Full Scale Range) of register MISC3 changes the full scale range of the A/D converter. A 0 in this
location sets the A/D full scale range at + 1 volt. A 1 in this location sets the A/D full scale range at + 0.25 volt. This
bit can be combined with the PSHG[2:0] to form a 4-bit control.
30
BIT:
SYMBOL:
TYPE:
DEFAULT:
BIT:
SYMBOL:
TYPE:
DEFAULT:
ADFSR
RENB
R/W
R/W
7
0
7
0
Reserved
Reserved
R/W
R/W
6
6
0
0
Reserved
Reserved
R/W
R/W
5
5
0
1
Reserved
Reserved
R/W
R/W
4
1
4
1
CKDLY3
PUD5*
ADDO
R/W
R/W
3
3
1
CLKOUTP
CKDLY2
R/W
R/W
2
0
2
0
201-0000-032 Rev 3.0, 6/2/99
Symbol:MISC2
Address:22h
Bits:7
Symbol:MISC3
Address:23h
Bits:6
CKDLY1
DVC
R/W
R/W
1
0
1
0
CH5001A
CKDLY0
MCF
R/W
R/W
0
1
0
1