CS42428 CIRRUS [Cirrus Logic], CS42428 Datasheet - Page 25

• Manufacturer Part Number: CS42428
• Description: 114 dB, 192kHz 8-Ch CODEC WITH PLL
• Manufacturer: CIRRUS [Cirrus Logic]

3.5.4.4
This One-Line Mode configuration can support up to 8 channels of DAC data on 2 DAC_SDIN pins, and
2 channels of ADC data and will handle up to 24-bit samples at a sampling frequency of 48 kHz on all
channels for both the DAC and ADC. The output data stream of the internal ADCs can be configured to
run at the DAC_SP clock speeds or to run at the ADC_SP rate. The DAC_SP and ADC_SP can operate at
different Fs rates.
Functional Mode Register (addr = 03h)
Interface Format Register (addr = 04h)
Misc. Control Register (addr = 05h)
ADC Mode
Set DAC_FMx = 00,01,10
Set ADC_FMx = 00,01,10
Set ADC_CLK_SEL = 0 or 1
Set DIFx bits to proper serial format
Set ADC_OLx bits = 00
Set DAC_OLx bits = 00,01,10
Set DAC_SP M/S = 0 or 1
Set ADC_SP M/S = 0 or 1
Set EXT ADC SCLK = 0
OLM Config #4
Register / Bit Settings
Not One
Line Mode
One Line
Mode #1
One Line
Mode #2
DAC_SCLK=64Fs/128Fs
DAC_LRCK=SSM/DSM/QSM
ADC_SCLK=64Fs/128Fs
ADC_LRCK=SSM/DSM/QSM
Not One Line Mode
not valid
not valid
RM CK
ADCIN1
ADCIN2
CS42428
Figure 16. OLM Configuration #4
ADC_SDOUT
DAC_SCLK
DAC_LRCK
DAC_SDIN1
DAC_SDIN2
DAC_SDIN3
DAC_SDIN4
ADC_SCLK
ADC_LRCK
Set ADC operating mode to Not One Line Mode since only 2 channels of
6 4Fs,12 8Fs , 256 Fs
DAC_LRCK can run at SSM, DSM, or QSM independent of ADC_LRCK
ADC_LRCK can run at SSM, DSM, or QSM independent of DAC_LRCK
Configure ADC_SDOUT to be clocked from the ADC_SP or DAC_SP
6 4Fs ,1 28Fs
DAC_SCLK=128Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=64Fs/128Fs
ADC_LRCK=SSM/DSM/QSM
Select DAC operating mode, see table below for valid combinations
Select the digital interface format when not in one line mode
One Line Mode #1
External ADCs are not used. Leave bit in default state.
Set DAC Serial Port to master mode or slave mode.
Set ADC Serial Port to master mode or slave mode.
M CLK
SCLK_PORT1
LRCK_PO RT1
SDIN_PORT 1
SDIN_PO RT2
SCLK_PO RT2
LRCK_PORT2
SDOUT1_PORT2
SDOUT2_PORT2
SDOUT3_PORT2
SDOUT4_PORT2
DIGITAL AUDIO
not valid
not valid
PRO CESSO R
DAC Mode
ADC are supported
Description
clocks.
DAC_SCLK=256Fs
DAC_LRCK=SSM
ADC_SCLK=64Fs/128Fs
ADC_LRCK=SSM/DSM/QSM
One Line Mode #2
not valid
not valid
CS42428
25