CS42428 CIRRUS [Cirrus Logic], CS42428 Datasheet - Page 26

• Manufacturer Part Number: CS42428
• Description: 114 dB, 192kHz 8-Ch CODEC WITH PLL
• Manufacturer: CIRRUS [Cirrus Logic]

3.6
The control port is used to access the registers, allowing the CS42428 to be configured for the desired op-
erational modes and formats. The operation of the control port may be completely asynchronous with re-
spect to the audio sample rates. However, to avoid potential interference problems, the control port pins
should remain static if no operation is required.
The control port has 2 modes: SPI and I
if there is a high to low transition on the AD0/CS pin, after the RST pin has been brought high. I
is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently se-
lecting the desired AD0 bit address state.
3.6.1
In SPI mode, CS is the CS42428 chip select signal, CCLK is the control port bit clock (input into the
CS42428 from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the
output data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling
edge.
Figure 17 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The
first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indi-
cator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),
which is set to the address of the register that is to be updated. The next eight bits are the data which will
be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z
state. It may be externally pulled high or low with a 47 kΩ resistor, if desired.
There is a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero,
the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will autoincrement
after each byte is read or written, allowing block reads or writes of successive registers.
To read a register, the MAP has to be set to the correct address by executing a partial write cycle which
finishes (CS high) immediately after the MAP byte. The MAP auto increment bit (INCR) may be set or
26
CS
C C L K
C D IN
C D O U T
Control Port Description and Timing
SPI Mode
ADDRESS
MAP = Memory Address Pointer, 8 bits, MSB first
1001111
C H IP
High Impedance
R/W
M A P
Figure 17. Control Port Timing in SPI Mode
MSB
b y te 1
2
C, with the CS42428 acting as a slave device. SPI mode is selected
DATA
b y te n
LSB
A D D R E S S
C H IP
1001111
R/W
MSB
LSB MSB
CS42428
LSB
2
C mode