CS42428 CIRRUS [Cirrus Logic], CS42428 Datasheet - Page 45
CS42428
Manufacturer Part Number
CS42428
Description
114 dB, 192kHz 8-Ch CODEC WITH PLL
Manufacturer
CIRRUS [Cirrus Logic]
Datasheet
1.CS42428.pdf
(67 pages)
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5.15
5.15.1 ADC LEFT CHANNEL GAIN (LGAINX)
5.16
5.16.1 ADC RIGHT CHANNEL GAIN (RGAINX)
5.17
5.17.1 SERIAL PORT SYNCHRONIZATION (SP_SYNC)
SP_SYNC
Reserved
Reserved
7
7
7
ADC Left Channel Gain (address 1Ch)
ADC Right Channel Gain (address 1Dh)
Interrupt Control (address 1Eh)
Default = 00h
Function:
Default = 00h
Function:
The level of the left analog channel can be adjusted in 1 dB increments as dictated by the Soft and
Zero Cross bits (SZC[1:0]) from +15 to -15 dB. Levels are decoded in two’s complement, as shown
in Table 16.
The level of the right analog channel can be adjusted in 1dB increments as dictated by the Soft and
Zero Cross bits (SZC[1:0]) from +15 to -15dB. Levels are decoded in two’s complement, as shown in
Table 16.
Default = 0
0 - DAC & ADC Serial Port timings not in phase
1 - DAC & ADC Serial Port timings are in phase
Function:
Forces the LRCK and SCLK from the DAC & ADC Serial Ports to align and operate in phase. This
function will operate when both ports are running at the same sample rate or when operating at dif-
ferent sample rates.
Reserved
Reserved
Reserved
6
6
6
Binary Code
001010
000101
000000
110001
110110
001111
111011
DE-EMPH1
RGAIN5
LGAIN5
Table 16. Example ADC Input Gain Settings
5
5
5
DE-EMPH0
RGAIN4
LGAIN4
Decimal Value
4
4
4
+15
+10
-10
-15
+5
-5
0
RGAIN3
LGAIN3
INT1
3
3
3
Volume Setting
+15 dB
+10 dB
-10 dB
-15 dB
RGAIN2
+5 dB
LGAIN2
-5 dB
0 dB
INT0
2
2
2
Reserved
RGAIN1
LGAIN1
1
1
1
CS42428
Reserved
RGAIN0
LGAIN0
0
0
0
45