RM5261A-300-HI PMC [PMC-Sierra, Inc], RM5261A-300-HI Datasheet - Page 13

• Manufacturer Part Number: RM5261A-300-HI
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002240, Issue 2
3.8
3.9
Table 1 Integer Multiply/Divide Operations
The baseline MIPS IV ISA specifies that the results of a multiply or divide operation be placed in
the Hi and Lo registers. These values can then be transferred to the general purpose register file
using the Move-from-Hi and Move-from-Lo ( MFHI / MFLO ) instructions.
In addition to the baseline MIPS IV integer multiply instructions, the RM5261A also implements
the 3-operand multiply instruction, MUL . This instruction specifies that the multiply result go
directly to the integer register file rather than the Lo register. The portion of the multiply that
would have normally gone into the Hi register is discarded. For applications where it is known that
the upper half of the multiply result is not required, using the MUL instruction eliminates the
necessity of executing an explicit MFLO instruction.
The multiply-add instructions, MAD and MADU , multiply two operands and add the resulting
product to the current contents of the Hi and Lo registers. The multiply-accumulate operation is
the core primitive of almost all signal processing algorithms, allowing the RM5261A to eliminate
the need for a separate DSP engine in many embedded applications.
Floating-Point Co-Processor
The RM5261A incorporates a high-performance fully pipelined floating-point co-processor which
includes a floating-point register file and autonomous execution units for multiply/add/convert and
divide/square root. The floating-point coprocessor is a tightly coupled execution unit, decoding
and executing instructions in parallel with, and in the case of floating-point loads and stores, in
cooperation with the integer unit. The superscalar capabilities of the RM5261A allow floating-
point computation instructions to issue concurrently with integer instructions.
Floating-Point Unit
The RM5261A floating-point execution unit supports single and double precision arithmetic, as
specified in the IEEE Standard 754. The execution unit is broken into a separate divide/square root
unit and a pipelined multiply/add unit. Overlap of the divide/square root and multiply/add
operations is supported.
The RM5261A maintains fully precise floating-point exceptions while allowing both overlapped
and pipelined operations. Precise exceptions are extremely important in object-oriented
programming environments and highly desirable for debugging in any environment.
Opcode
MULT/U,
MAD/U
MUL
DMULT,
DMULTU
DIV, DIVD
DDIV,
DDIVU
Operand
Size
16 bit
32 bit
16 bit
32 bit
any
any
any
Latency
3
4
3
4
7
36
68
RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet
Repeat
Rate
2
3
2
3
6
36
68
Stall
Cycles
0
0
1
2
0
0
0
Preliminary
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