RM5261A-300-HI PMC [PMC-Sierra, Inc], RM5261A-300-HI Datasheet - Page 35

• Manufacturer Part Number: RM5261A-300-HI
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002240, Issue 2
9.3
9.4
System Interface Parameters
Boot-Time Interface Parameters
Parameter
Data Output
Data Setup
Data Hold
Notes
1.
2.
3.
4.
5.
6.
Parameter
Mode Data Setup
Mode Data Hold
Timings are measured from 0.425 x VccIO of clock to 0.425 x VccIO of signal for 3.3V I/O.
Timings are measured from 0.48 x VccIO of clock to 0.48 x VccIO of signal for 2.5V I/O.
Capacitive load for all maximum output timings is 50 pF. Minimum output timings are for
theoretical no load condition-untested.
Data Output timing applies to all signal pins whether tristate I/O or output only.
Setup and Hold parameters apply to all signal pins whether tristate I/O or input only.
Only mode 14:13 = 10 is tested and guaranteed.
Data shown is for 3.3 V I/O. For 2.5 V I/O derate all times by .5 nS.
4
4
1
2,3
Symbol Conditions
t
t
t
DO
DS
DH
6
Symbol
t
t
DS
DH
mode14..13 = 10
mode14..13 = 01
t
t
rise
fall
= see above table
= see above table
RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet
Min
4
0
5,6
5,6
(fastest)
(slowest)
1
CPU Speed
Min
1.0
1.0
2.5
1.0
250 MHz to 350 MHz
Max
Max
5.0
6.0
Units
SysClock cycles
SysClock cycles
Units
ns
ns
ns
ns
Preliminary
35