RM5261A-300-HI PMC [PMC-Sierra, Inc], RM5261A-300-HI Datasheet - Page 18

• Manufacturer Part Number: RM5261A-300-HI
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002240, Issue 2
3.14 Joint TLB
3.15 Instruction TLB
For fast virtual-to-physical address translation, the RM5261A uses a large, fully associative TLB
that maps 96 virtual pages to their corresponding physical addresses. As indicated by its name, the
joint TLB (JTLB) is used for both instruction and data translations. The JTLB is organized as 48
pairs of even-odd entries, and maps a virtual address and address space identifier into the large, 64
GB physical address space.
Two mechanisms are provided to assist in controlling the amount of mapped space and the
replacement characteristics of various memory regions. First, the page size can be configured, on a
per-entry basis, to use page sizes in the range of 4 KB to 16 MB (in multiples of 4). The CP0 Page
Mask register is loaded with the desired page size of a mapping, and that size is stored into the
TLB along with the virtual address when a new entry is written. Thus, operating systems can
create special purpose maps; for example, an entire frame buffer can be memory mapped using
only one TLB entry.
The second mechanism controls the replacement algorithm when a TLB miss occurs. The
RM5261A provides a random replacement algorithm to select a TLB entry to be written with a
new mapping; however, the processor also provides a mechanism whereby a system specific
number of mappings can be locked into the TLB, thereby avoiding random replacement. This
mechanism uses the Wired register and allows the operating system to guarantee that certain pages
are always mapped for performance reasons and for deadlock avoidance. This mechanism also
facilitates the design of real-time systems by allowing deterministic access to critical software.
The JTLB also contains information that controls the cache coherency protocol for each page.
Specifically, each page has attribute bits to determine whether the coherency algorithm is one of
the following:
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•
•
•
•
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The non-coherent protocols are used for both code and data on the RM5261A, with data using
write-back or write-through depending on the application.
The coherency attributes generate coherent transaction types on the system interface. However, in
the RM5261A cache coherency is not supported. Hence the coherency attributes should never be
used.
The RM5261A implements a 2-entry instruction TLB (ITLB) to minimize contention for the
JTLB, eliminate the timing critical path of translating through a large associative array, and save
power. Each ITLB entry maps a 4 KB page. The ITLB improves performance by allowing
instruction address translation to occur in parallel with data address translation. When a miss
uncached
non-coherent write-back
non-coherent write-through with write-allocate
non-coherent write-through without write-allocate
sharable
exclusive
update
RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet
Preliminary
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