RM5261A-300-HI PMC [PMC-Sierra, Inc], RM5261A-300-HI Datasheet - Page 22

• Manufacturer Part Number: RM5261A-300-HI
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002240, Issue 2
3.22 System Address/Data Bus
3.23 System Command Bus
3.24 Handshake Signals
Figure 6
The 64-bit System Address Data (SysAD) bus is used to transfer addresses and data between the
RM5261A and the rest of the system. It is protected with an 8-bit parity check bus (SysADC). The
system interface is configurable to allow easy interfacing to memory and I/O systems of varying
frequencies.
The Block Write data rate, Non-block Write protocol, and the Output Drive strength are
programmable at Boot time via the Mode Control bits. The rate at which the processor receives
data is also fully controlled by the external device.
The RM5261A interface has a 9-bit System Command (SysCmd) bus. The command bus
indicates whether the SysAD bus carries address or data information on a per-clock basis. If the
SysAD carries address, the SysCmd bus indicates what type of transaction is to take place (for
example, a read or write). If the SysAD carries data, the SysCmd bus provides information about
the data (for example, this is the last data word transmitted, or the data contains an error). The
SysCmd bus is bidirectional to support both processor requests and external requests to the
RM5261A. Processor requests are initiated by the RM5261A and responded to by an external
device. External requests are issued by an external device and require the RM5261A to respond.
The RM5261A supports one- to eight-byte transfers as well as block transfers on the SysAD bus.
In the case of a sub-double word transfer, the three low-order address bits give the byte address of
the transfer, and the SysCmd bus indicates the number of bytes being transferred.
There are six handshake signals on the system interface. Two of these, RdRdy* and WrRdy*, are
used by an external device to indicate to the RM5261A whether it can accept a new read or write
transaction. The RM5261A samples these signals before deasserting the address on read and write
requests.
RM5261A
Typical Embedded System Block Diagram
DRAM
Latch
72
72
23
RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet
Address
Control
Memory I/O
Controller
Flash/
Boot
Rom
8
x
PCI Bus
x
Preliminary
22