RM5261A-300-HI PMC [PMC-Sierra, Inc], RM5261A-300-HI Datasheet - Page 24

• Manufacturer Part Number: RM5261A-300-HI
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002240, Issue 2
3.26 Enhanced Write Modes
3.27 External Requests
Figure 8
The RM5261A implements two enhancements to the original R4000 write mechanism: Write
Reissue and Pipeline Writes. The original R4000 allowed a write address cycle on the SysAD bus
only once every four SysClock cycles. Hence for a non-block write, this meant that two out of
every four cycles were wait states.
Pipelined write mode eliminates these two wait states by allowing the processor to drive a new
write address onto the bus immediately after the previous write data cycle. This allows for higher
SysAD bus utilization. However, at high bus frequencies the processor may drive a subsequent
write onto the bus prior to the time the external agent deasserts WrRdy*, indicating that it can not
accept another write cycle. This can cause the write cycle to be missed.
Write reissue mode is an enhancement to pipelined write mode and allows the processor to reissue
missed write cycles. If WrRdy* is deasserted during the issue phase of a write operation, the cycle
is aborted by the processor and reissued at a later time.
In write reissue mode, a write rate of one write every two bus cycles can be achieved. Pipelined
writes have the same two bus cycle write repeat rate, but can issue one additional write following
the deassertion of WrRdy*.
The External Request pin, ExtRqst*, is asserted by the external agent when it requires mastership
of the system interface, either to perform an independent transfer or to write to the interrupt
register within the RM5261A. An independent transfer is a data transfer between two external
agents or between an external agent and memory or peripheral on the system interface. Following
the asserting of the ExtRqst*, the RM5261A tri-states its drivers allowing the external agent to
use the system interface buses to complete an independent transfer. The external agent is
responsible for returning mastership of the system interface to the RM5261A when it has
completed the independent transfer and does so by executing an External Null cycle.
SysClock
SysAD
SysCmd
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
Processor Block Write
Write
Addr
NData
Data0
NData
Data1
RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet
Data2
NData
NEOD
Data3
Preliminary
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