RM5261A-300-HI PMC [PMC-Sierra, Inc], RM5261A-300-HI Datasheet - Page 21

• Manufacturer Part Number: RM5261A-300-HI
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002240, Issue 2
3.20 Write buffer
3.21 System Interface
Table 3 Cache Attributes
Writes to external memory, whether cache miss write-backs or stores to uncached or write-through
addresses, use the on-chip write buffer. The write buffer holds up to four 64-bit address and data
pairs. The entire buffer is used for a data cache write-back and allows the processor to proceed in
parallel with the memory update. For uncached and write-through stores, the write buffer
significantly increases performance by decoupling the
execution stream.
The system interface consists of a 64-bit Address/Data bus with 8 parity check bits and a 9-bit
command bus. In addition, there are 6 handshake signals and 6 interrupt inputs. The interface is
capable of transferring data between the processor and memory at a peak rate of 800MB/sec with a
100MHz SysClock.
Figure 6 shows a typical embedded system using the RM5261A. In this example, a bank of
DRAMs and a memory controller ASIC share the processor’s
controller provides separate ports to a boot ROM and an I/O system.
Characteristics
Size
Organization
Line size
Index
Tag
Write policy
Read order
Write order
miss restart after transfer of
Parity
Cache locking
Instruction
32KB
32B
vAddr
pAddr
n.a.
sub-block
entire line
per-word
set A
2-way set associative
sequential
RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet
11..0
31..12
SysAD
SysAD
bus transfers from the instruction
Data
32KB
2-way set associative
32B
vAddr
pAddr
write-back/write-through
sub-block
sequential
first double
per-byte
set A
bus while the memory
11..0
31..12
Preliminary
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