W83194R-67B Winbond, W83194R-67B Datasheet - Page 2

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W83194R-67B

Manufacturer Part Number
W83194R-67B
Description
100MHZ 3-DIMM CLOCK FOR VIA MVP4
Manufacturer
Winbond
Datasheet
3.0 BLOCK DIAGRAM
4.0 PIN CONFIGURATION
*CPU_STOP#
*PCI_STOP#
BUFFER IN
PCICLK_F/ *MODE
* PCI_STOP#/REF0
SDCLK*
SDATA*
FS(0:3)*
MODE*
PCICLK0/ *FS3
Xout
Xin
BUFFER IN
SDRAM11
SDRAM10
PCICLK2
PCICLK3
PCICLK4
SDRAM 9
SDRAM 8
PCICLK1
*SDATA
*SCLK
Vddq2
Vddq3
Vddq1
Vddq2
4
Xout
Vss
Vss
Vss
Vss
Xin
PLL2
Spectrum
POR
Spread
PLL1
XTAL
OSC
~
LATCH
Control
Config.
16
14
21
Logic
10
11
12
13
15
17
18
19
20
22
23
24
Reg.
1
2
3
4
6
7
9
5
8
~
4
- 2 -
PCI
Clock
Divider
1/2
STOP
STOP
STOP
42
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
41
40
39
38
37
36
35
SDRAM 1
48MHz/ *FS0
24MHz/ *FS1
SDRAM_F
SDRAM 0
SDRAM 2
SDRAM 3
SDRAM 4
SDRAM 5
Vddq3
SDRAM 6
SDRAM 7
Vddq4
CPUCLK1
Vddq3
Vss
REF1/ *FS2
VddL1
CPUCLK_F
CPUCLK0
Vss
CPUCLK2
*CPU_STOP#
Vss
Publication Release Date: Dec.. 1999
12
5
2
3
48MHz
24MHz
REF(0:1)
CPUCLK_F
CPUCLK(0:2)
SDRAM_F
SDRAM(0:11)
PCICLK(0:4)
PCICLK_F
W83194R-67B
PRELIMINARY
Revision 0.50

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