MM908E624ACDWB/R Motorola, MM908E624ACDWB/R Datasheet - Page 21

• Manufacturer Part Number: MM908E624ACDWB/R
• Description: TRIPLE HIGH-SIDE SWITCH WITH EMBEDDED MCU AND LIN
• Manufacturer: Motorola

Table 6. Operating Modes Overview
INTERRUPTS
interrupt sources. An interrupt pulse on the
generated to report a fault to the MCU. All interrupts are not
maskable and cannot be disabled.
is set, indicating the source of the event. This interrupt source
information is only transferred once, and the INTSRC bit is
cleared automatically.
Low-Voltage Interrupt
voltage VSUP1. If this voltage falls below the LVI threshold,
it will set the LVF bit in the SPI Status register and an interrupt
will be initiated. The LVF bit remains set as long as the Low-
voltage condition is present.
circuitry is disabled.
High-Voltage Interrupt
voltage VSUP1. If this voltage rises above the HVI threshold,
it will set the HVF bit in the SPI Status register and an
interrupt will be initiated. The HVF bit remains set as long as
the high-voltage condition is present.
circuitry is disabled.
Wake-Up Interrupts
on the L1, L2, or the LIN bus to the MCU. All wake-up
interrupts are not maskable and cannot be disabled.
Analog Integrated Circuit Device Data
Freescale Semiconductor
Request
Device
Normal
Normal
In Normal (Run) mode the 908E624 has four different
After an Interrupt the INTSRC bit in the SPI Status register
Low-voltage interrupt (LVI) is related to external supply
During Sleep and Stop mode the low-voltage interrupt
High-voltage interrupt (HVI) is related to external supply
During Sleep and Stop mode the low-voltage interrupt
In Stop mode the
Mode
Reset
(Run)
Sleep
Stop
V
Voltage Regulator
DD
current capability
ON with limited
V
V
V
V
DD
DD
DD
DD
IRQ_A
OFF
ON
ON
ON
terminal reports wake-up events
L1, L2 state change,
L1, L2 state change
SS
LIN wake-up,
Capabilities
LIN wake-up
Wake-Up
rising edge
N/A
N/A
N/A
IRQ_A
terminal is
Output
RST_A
HIGH
HIGH
HIGH
LOW
LOW
150 ms time out if
Window WD if
WD enabled
Peripheral Interface (SPI) Status register is set, indicating the
source of the event. This wake-up source information is only
transferred once, and the INTSRC bit is cleared
automatically.
procedure.
VOLTAGE REGULATOR TEMPERATURE
PREWARNING (VDDT)
generated if the voltage regulator temperature is above the
T
register and an interrupt will be initiated. The VDDT bit
remains set as long as the error condition is present.
temperature prewarning circuitry is disabled.
HIGH-SIDE SWITCH THERMAL SHUTDOWN
(HSST)
generated if one of the high-side switches HS1:HS3 is above
the HSST threshold, it will shutdown the corresponding High-
side switch, set the HSST flag in the SPI Status register and
an interrupt will be initiated. The HSST bit remains set as long
as the error condition is present.
shutdown circuitry is disabled.
Watchdog
Function
PRE
Disabled
Disabled
Disabled
enabled
After a wake-up interrupt, the INTSRC bit in the Serial
Figure
Voltage regulator temperature prewarning (VDDT) is
During Sleep and Stop mode the voltage regulator
The high-side switch thermal shutdown HSST is
During Sleep and Stop mode the high-side switch thermal
threshold, it will set the VDDT bit in the SPI Status
11, page 22, describes the Stop/Wake-Up
HS1, HS2,
and HS3
Disabled
Disabled
Disabled
Enabled
Enabled
Recessive state with
Recessive state with
wake-up capability
wake-up capability
Recessive only
LIN Interface
Transmit and
Transmit and
Functional Device Operation
receive
receive
Functional Description
Not active
Not active
Not active
Not active
Amplifier
Sense
Active
908E624
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