MM908E624ACDWB/R Motorola, MM908E624ACDWB/R Datasheet - Page 26

• Manufacturer Part Number: MM908E624ACDWB/R
• Description: TRIPLE HIGH-SIDE SWITCH WITH EMBEDDED MCU AND LIN
• Manufacturer: Motorola

SPI REGISTER OVERVIEW
value, and bit reset condition.
.
Table 7. SPI Register Overview
SPI Control Register (Write)
Table 8. Control Bits Function (Write Operation)
LINSL2:1—LIN Baud Rate and Low-Power Mode
Selection Bits
power mode in accordance with
LINSL2:1 bits.
Table 9. LIN Baud Rate and Low-Power Mode Selection
LIN-PU—LIN Pullup Enable Bit
Stop modes.
26
908E624
Functional Description
Functional Device Operation
Notes
LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1
LINSL2
30.
31.
Write Reset Condition
D7
Table 7
Table 8
These bits select the LIN slew rate and requested low-
This bit controls the LIN pullup resistor during Sleep and
• 1 = Pullup disconnected in Sleep and Stop modes.
• 0 = Pullup connected in Sleep and Stop modes.
Write Reset Value
0
0
1
1
Information
Read/Write
D7 signals interrupts and wake-up interrupts, D6:D0 indicated the source.
The first SPI read after reset returns the BATFAIL flag state on bit D4.
Read
Write
Bits
D6
summarizes the SPI Register bit meaning, reset
shows the SPI Control register bits by name.
LINSL1
0
1
0
1
D5
Low-Power Mode (Sleep or Stop) Request
D4
INTSRC
Baud Rate up to 20 kbps (normal)
Baud Rate up to 10 kbps (slow)
LINSL2
RESET
POR,
D7
Baud Rate up to 100 kbps
0
Fast Program Download
D3
Table
(30)
Description
9. Reset clears the
LINFAIL
LINSL1
RESET
D2
LINWU
POR,
D6
or
0
D1
LIN-PU
POR
HVF
D5
D0
0
POR, RESET
BATFAIL
HS3ON
HS3ON:HS1ON—High-Side H3:HS1 Enable Bit
terminal must be connected to the VDD terminal.
MODE2:1—Mode Section Bits
watchdog in accordance with
Table 10. Mode Selection Bits
these modes are not affected by noise issue during SPI
transmission, the Sleep/Stop commands require two SPI
transmissions.
Notes
LVF
D4
32.
33.
MODE2
or
0
This bit enables the HSx. Reset clears the HSx bit.
• 1 = HSx switched on (refer to Note below).
• 0 = HSx switched off.
Note If no PWM on HS1 and HS2 is required, the PWMIN
The MODE2:1 bits control the operating modes and the
To safely enter Sleep or Stop mode and to ensure that
0
0
1
1
(31)
To enter Sleep and Stop mode, a special sequence of SPI
commands is implemented.
The device stays in Run (Normal) mode.
Bit
MODE1
HS2ON
RESET
VDDT
POR,
D3
0
0
1
0
1
Analog Integrated Circuit Device Data
HS1ON
RESET
HSST
POR,
D2
0
Table
Watchdog Clear
Run (Normal) Mode
Sleep Mode
Stop Mode
Freescale Semiconductor
Description
10.
MODE2
D1
L2
—
—
(32)
(32)
(33)
MODE1
D0
L1
—
—