MM908E625ACDWB/R2 Motorola, MM908E625ACDWB/R2 Datasheet - Page 21

• Manufacturer Part Number: MM908E625ACDWB/R2
• Description: Integrated Quad Half H-Bridge with Power Supply / Embedded MCU / and LIN Serial Communication
• Manufacturer: Motorola

HVRE—High-Voltage Reset Enable Bit
conditions. Reset clears the HVRE bit.
communication link between the microcontroller and the
908E625.
prepared. The falling edge on the
a new data transfer and puts MISO in the low-impedance mode.
The first valid data are moved to MISO with the rising edge of
SPSCK.
The MOSI input is sampled on a falling edge of SPSCK. The
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
SPSCK
MOSI
MISO
This read/write bit enables resets on high-voltage
The serial peripheral interface (SPI) creates the
The interface consists of four terminals (see
•
• MOSI—Master-Out Slave-In
• MISO—Master-In Slave-Out
• SPSCK—Serial Clock
During the inactive phase of
The MISO output changes data on a rising edge of SPSCK.
SS
1 = High-voltage reset enabled.
0 = High-voltage reset disabled.
SS
Rising edge of SPSCK
—Slave Select
Change MISO/MOSI
Output
R/W
S7
Falling edge of SPSCK
Sample MISO/MOSI
Input
SS
A4
S6
SS
, the new data transfer is
Read/Write, Address, Parity
Freescale Semiconductor, Inc.
A3
S5
System Status Register
line indicates the start of
For More Information On This Product,
A2
S4
SERIAL PERIPHERAL INTERFACE
A1
S3
Figure
Go to: www.freescale.com
A0
S2
9):
Figure 9. SPI Protocol
Slave latch
register address
S1
P
S0
X
HTRE—High-Temperature Reset Enable Bit
conditions. Reset clears the HTRE bit.
master sends address and data, slave system status, and data
of the selected address.
data transfer is only valid if exactly 16 sample clock edges are
present in the active phase of
the register by the rising edge of
internally latched into the SPI at the time when the parity bit is
transferred.
This read/write bit enables resets on high-temperature
• 1 = High-temperature reset enabled.
• 0 = High-temperature reset disabled.
A complete data transfer via the SPI
After a write operation, the transmitted data is latched into
SS
D7
D7
HIGH forces MISO to high impedance.
D6
D6
D5
D5
Data (Register write)
Data (Register read)
D4
D4
SS
SS
.
D3
D3
. Register read data is
D2
D2
consists
D1
D1
of 2 bytes. The
D0
D0
Slave latch
data
908E625
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