MM908E625ACDWB/R2 Motorola, MM908E625ACDWB/R2 Datasheet - Page 36

• Manufacturer Part Number: MM908E625ACDWB/R2
• Description: Integrated Quad Half H-Bridge with Power Supply / Embedded MCU / and LIN Serial Communication
• Manufacturer: Motorola

Autonomous Watchdog (AWD)
functions:
AWDCTL Register is set. If these bits are cleared, the AWD
oscillator is disabled and the watchdog switched off.
Watchdog
setting the AWDRE bit, watchdog functionality in RUN mode is
activated. Once this function is enabled, it is not possible to
disable it via software.
reset is initiated. Operations of the watchdog function cease in
STOP mode. Normal operation will be continued when the
system is back to RUN mode.
must be reset before it reaches the end value. This is done by
a write to the AWDRST bit in the AWDCTL Register.
Periodic Interrupt
enabled by setting the AWDIE bit in the AWDCTL Register. If
AWDIE is set, the AWD wakes up the system after a fixed
period of time. This time period can be selected with bit AWDR
in the AWDCTL Register.
Cyclic Wake-Up
If this feature is enabled, the selected Hall-effect sensor input
terminals are switched on and sensed. If a “1” is detected on
one of these inputs and the interrupt for the Hall-effect sensors
is enabled, a system wake-up is performed. (Switch on main
voltage regulator and assert
Autonomous Watchdog Control Register (AWDCTL)
AWDRST—Autonomous Watchdog Reset Bit
period. AWDRST always reads 0. Reset clears AWDRST bit.
908E625
36
Reset
Read
Write
The Autonomous Watchdog module consists of three
• Watchdog function for the CPU in RUN mode
• Periodic interrupt function in STOP mode
• Cyclic wake-up function in STOP mode
The AWD is enabled if AWDIE, AWDRE, or AWDCC in the
The watchdog function is only available in RUN mode. On
If the timer reaches end value and AWDRE is set, a system
To prevent a watchdog reset, the watchdog timeout counter
Periodic interrupt is only available in STOP mode. It is
The cyclic wake-up feature is only available in STOP mode.
This write-only bit resets the Autonomous Watchdog timeout
• 1 = Reset AWD and restart timeout period.
• 0 = No effect.
Bit7
0
0
Register Name and Address: AWDCTL - $0a
6
0
0
AWDRST
5
0
0
IRQ_A
ADRE
4
0
AWDIE AWDCC
to the microcontroller).
3
0
Freescale Semiconductor, Inc.
For More Information On This Product,
2
0
AWDF AWDR
1
0
Go to: www.freescale.com
Bit0
0
AWDRE—Autonomous Watchdog Reset Enable Bit
on the
AWDRE is one-time setable (write once) after each reset. Reset
clears the AWDRE bit.
AWDIE—Autonomous Watchdog Interrupt Enable Bit
Autonomous Watchdog timeout flag, AWFD.
asserted when the device is in STOP mode. Reset clears the
AWDIE bit.
AWDCC— Autonomous Watchdog Cyclic Check
terminal Hall-effect sensor and the analog inputs. Reset clears
the AWDCC bit.
AWDF—Autonomous Watchdog Timeout Flag Bit
has timed out. Clear AWDF by writing a logic [1] to AWDF.
Clearing AWDF also resets the AWD counter and starts a new
timeout period. Reset clears the AWDF bit. Writing a logic [0] to
AWDF has no effect.
AWDR—Autonomous Watchdog Rate Bit
Watchdog. Reset clears the AWDR bit.
Voltage Regulator
regulator to provide internal power and external power for the
MCU. The on-chip regulator consist of two elements, the main
voltage regulator and the low-voltage reset circuit.
provides a regulated V
device. The output of the regulator is also connected to the VDD
terminal to provide the 5.0 V to the microcontroller.
This read/write bit enables resets on AWD timeouts. A reset
• 1 = Autonomous watchdog enabled.
• 0 = Autonomous watchdog disabled.
This read/write bit enables CPU interrupts by the
• 1 = CPU interrupt requests from AWDF enabled.
• 0 = CPU interrupt requests from AWDF disabled.
This read/write bit enables the cyclic check of the two-
• 1 = Cyclic check of the Hall-effect sensor and analog port.
• 0 = No cyclic check of the Hall-effect sensor and analog
This read/write flag is set when the Autonomous Watchdog
• 1 = AWD has timed out.
• 0 = AWD has not yet timed out.
This read/write bit selects the clock rate of the Autonomous
• 1 = Fast rate selected (10 ms).
• 0 = Slow rate selected (20 ms).
The 908E625 chip contains a low-power, low-drop voltage
The V
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
port.
RST_A
DD
regulator accepts a unregulated input supply and
is only asserted when the device is in RUN mode.
DD
supply to all digital sections of the
IRQ_A
is only