S29PL-N_07 SPANSION [SPANSION], S29PL-N_07 Datasheet - Page 32

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S29PL-N_07

Manufacturer Part Number
S29PL-N_07
Description
256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
Manufacturer
SPANSION [SPANSION]
Datasheet
32
7.4.4
Chip Erase Command Sequence
Chip erase is a six-bus cycle operation as indicated by
Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The Embedded
Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any controls or timings during these operations. The
Command Definition tables
requirements for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no
longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. See
Write Operation Status on page 37
Any commands written during the chip erase operation are ignored. However, note that a hardware reset
immediately terminates the erase operation. If that occurs, the chip erase command sequence should be
reinitiated once that bank has returned to reading array data, to ensure data integrity.
Software Functions and Sample Code
The following is a C source code example of using the chip erase function. Refer to the Spansion Low Level
Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash memory
software development guidelines.
/* Example: Chip Erase Command */
/* Note: Cannot be suspended
*((UINT16 *)base_addr + 0x555) = 0x00AA;
*((UINT16 *)base_addr + 0x2AA) = 0x0055;
*((UINT16 *)base_addr + 0x555) = 0x0080;
*((UINT16 *)base_addr + 0x555) = 0x00AA;
*((UINT16 *)base_addr + 0x2AA) = 0x0055;
*((UINT16 *)base_addr + 0x000) = 0x0010;
Cycle
1
2
3
4
5
6
Chip Erase Command
Setup Command
Description
Unlock
Unlock
Unlock
Unlock
(Table 12.1 on page 66
S29PL-N MirrorBit
D a t a
for information on these status bits.
(LLD Function = lld_ChipEraseCmd)
*/
S h e e t
Table 7.10 Chip Erase
Operation
Write
Write
Write
Write
Write
Write
Flash Family
and
( P r e l i m i n a r y )
Table 12.1 on page
/* write unlock cycle 1
/* write unlock cycle 2
/* write setup command
/* write additional unlock cycle 1 */
/* write additional unlock cycle 2 */
/* write chip erase command
Table 12.2 on page
Word Address
Base + 2AAh
Base + 2AAh
Base + 555h
Base + 555h
Base + 555h
Base + 555h
66. These commands invoke the
68) show the address and data
S29PL-N_00_A5 June 6, 2007
00AAh
00AAh
0055h
0080h
0055h
0010h
*/
*/
*/
*/
Data

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