S29PL-N_07 SPANSION [SPANSION], S29PL-N_07 Datasheet - Page 42

• Manufacturer Part Number: S29PL-N_07
• Description: 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
• Manufacturer: SPANSION [SPANSION]

7.6
7.7
42
Writing Commands/Command Sequences
Hardware Reset
During a write operation, the system must drive CE# and WE# to V
address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is
latched on the 1st rising edge of WE# or CE#. An erase operation can erase one sector, multiple sectors, or
the entire device.
sector occupies. The device address space is divided into four banks: Banks B and C contain only 128 Kword
sectors, while Banks A and D contain both 32 Kword boot sectors in addition to 128 Kword sectors. A bank
address is the set of address bits required to uniquely select a bank. Similarly, a sector address is the
address bits required to uniquely select a sector. I
current specification for the write mode. See
tables and timing diagrams for write operations.
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET#
is driven low for at least a period of t
all outputs, and ignores all read/write commands for the duration of the RESET# pulse. The device also
resets the internal state machine to reading array data.
To ensure data integrity the operation that was interrupted should be reinitiated once the device is ready to
accept another command sequence.
When RESET# is held at V
not at V
RESET# may be tied to the system reset circuitry which enables the system to read the boot-up firmware
from the Flash memory upon a system reset.
See
V
V
CC
SS
Figure 11.5 on page 56
SS
WP#/ACC
RESET#
DQ0 – DQ15
A21 – A0
A21 – A0
A21 – A0
, the standby current is greater.
CE1#
CE2#
WE#
Figure 7.6 Simultaneous Operation Block Diagram for S29PL129N
Table 6.1 on page 18
Command
Register
Control
State
and
SS
and
Mux
Mux
S29PL-N MirrorBit
, the device draws CMOS standby current (I
D a t a
Figure 11.8 on page 60
RP
CE1# = L
CE2# = H
CE1# = H
CE2# = L
Bank 1A Address
, the device immediately terminates any operation in progress, tristates
Bank 1B Address
Bank 2B Address
and
Bank 2A Address
RY/BY#
S h e e t
Table 6.2 on page 19
AC Characteristics on page 59
™
Flash Family
CC2
Control
Status
in
( P r e l i m i n a r y )
DC Characteristics on page 57
for timing diagrams.
X-Decoder
X-Decoder
X-Decoder
X-Decoder
Bank 1A
Bank 1B
Bank 2A
Bank 2B
indicate the address space that each
IL
and OE# to V
CC4
contains timing specification
). If RESET# is held at V
S29PL-N_00_A5 June 6, 2007
IH
when providing an
represents the active
Mux
OE#
DQ15 – DQ0
IL
, but