S29PL-N_07 SPANSION [SPANSION], S29PL-N_07 Datasheet - Page 40

• Manufacturer Part Number: S29PL-N_07
• Description: 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
• Manufacturer: SPANSION [SPANSION]

Notes
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more
2. DQ7 a valid address when reading status information. Refer to the appropriate subsection for further details.
3. Data are invalid for addresses in a Program Suspended sector.
4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations.
5. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer Programming indicates the data-bar
7.5
40
Program
Suspend
Mode
(Note 3)
Erase
Suspend
Mode
Write to
Buffer
(Note 5)
information.
for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location.
Reading within Program
Suspended Sector
Reading within Non-Program
Suspended Sector
Erase-Suspend-
Read
Erase-Suspend-Program
BUSY State
Exceeded Timing Limits
ABORT State
Simultaneous Read/Write
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a 1, indicating that the program or erase cycle was not successfully
completed. The device may output a 1 on DQ5 if the system tries to program a 1 to a location that was
previously programmed to 0. Only an erase operation can change a 0 back to a 1, Under this condition, the
device halts the operation, and when the timing limit has been exceeded, DQ5 produces a 1. Under both
these conditions, the system must write the reset command to return to the read mode (or to the erase-
suspend-read mode if a bank was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timeout State Indicator
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors
are selected for erasure, the entire time-out also applies after each additional sector erase command. When
the time-out period is complete, DQ3 switches from a 0 to a 1. If the time between additional sector erase
commands from the system can be assumed to be less than t
Sector Erase Command Sequence for more details.
After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is
1, the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until
the erase operation is complete. If DQ3 is 0, the device accepts additional sector erase commands. To
ensure the command has been accepted, the system software should check the status of DQ3 prior to and
following each sub-sequent sector erase command. If DQ3 is high on the second status check, the last
command might not have been accepted.
DQ1: Write to Buffer Abort
DQ1 indicates whether a Write to Buffer operation was aborted. Under these conditions DQ1 produces a 1.
The system must issue the Write to Buffer Abort Reset command sequence to return the device to reading
array data. See Write Buffer Programming Operation for more details.
The simultaneous read/write feature allows the host system to read data from one bank of memory while
programming or erasing another bank of memory. An erase operation may also be suspended to read from or
program another location within the same bank (except the sector being erased).
Read/Write Cycle Timings on page 63
Status
Erase Suspended Sector
Non-Erase
Suspended Sector
Table 7.18 Write Operation Status
(Not Allowed)
S29PL-N MirrorBit
(Note 2)
INVALID
DQ7#
DQ7#
DQ7#
DQ7#
D a t a
DQ7
Data
Data
1
shows how read and write cycles may be initiated for simultaneous
S h e e t
Table 7.18
(Not Allowed)
No Toggle
INVALID
Toggle
Toggle
Toggle
Toggle
Data
Data
DQ6
™
Flash Family
shows the status of DQ3 relative to the other status bits.
( P r e l i m i n a r y )
(Not Allowed)
INVALID
(Note 1)
DQ5
Data
Data
0
0
0
1
0
SEA
, the system need not monitor DQ3. See
(Not Allowed)
INVALID
Data
Data
DQ3
N/A
N/A
N/A
N/A
N/A
S29PL-N_00_A5 June 6, 2007
Figure 11.12, Back-to-back
(Not Allowed)
INVALID
(Note 2)
Toggle
DQ2
Data
Data
N/A
N/A
N/A
N/A
(Not Allowed)
(Note 4)
INVALID
DQ1
Data
Data
N/A
N/A
0
0
1