CY7C1363C CYPRESS [Cypress Semiconductor], CY7C1363C Datasheet - Page 10

• Manufacturer Part Number: CY7C1363C
• Description: 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05541 Rev. *A
ZZ Mode Electrical Characteristics
Truth Table
I
t
t
t
t
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Sleep Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Notes:
DDZZ
ZZS
ZZREC
ZZI
RZZI
3. X=”Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals , BWE, GW = H..
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE
Parameter
the ADSP or with the assertion of ADSC . As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a don't
care for the remainder of the write cycle.
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Cycle Description
[ 3, 4, 5, 6, 7]
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Address
External
External
External
External
External
Current
Current
Current
Current
Current
Current
Description
Used
None
None
None
None
None
None
Next
Next
Next
Next
Next
Next
CE
H
H
H
H
H
H
H
X
X
L
L
L
L
X
X
X
X
X
X
L
L
L
L
1
PRELIMINARY
CE
H
H
H
H
H
X
X
X
L
X
L
X
X
X
X
X
X
X
X
X
X
X
X
2
CE
X
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
3
ZZ
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
ADSP
Test Conditions
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
DD
DD
L
L
L
L
– 0.2V
– 0.2V
ADSC
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
L
L
L
L
L
L
ADV WRITE OE CLK
X
. Writes may occur only on subsequent clocks after
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
2t
L
L
L
L
L
Min.
CYC
0
H
H
H
H
H
H
X
X
X
X
X
X
L
X
L
L
L
X
X
L
L
X
X
CY7C1361C
CY7C1363C
2t
2t
Max.
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
35
X
CYC
CYC
Page 10 of 30
three-state
three-state
three-state
three-state
three-state
three-state
three-state
three-state
three-state
three-state
three-state
three-state
DQ
Q
D
Q
Q
Q
D
D
Q
Q
D
D
Unit
mA
ns
ns
ns
ns