CY7C1363C CYPRESS [Cypress Semiconductor], CY7C1363C Datasheet - Page 23

• Manufacturer Part Number: CY7C1363C
• Description: 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05541 Rev. *A
Timing Diagrams
Write Cycle Timing
Notes:
23. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
Data Out (Q)
Data in (D)
ADDRESS
BWE,
BW
ADSP
ADSC
GW
ADV
CE
CLK
OE
X
BURST READ
High-Z
t ADS
t CES
[22, 23]
t AS
A1
(continued)
t ADH
t CEH
t
t AH
t
CH
OEHZ
Byte write signals are ignored for first cycle when
ADSP initiates burst
t CYC
t ADS
t
Single WRITE
CL
t
DS
D(A1)
t ADH
t
DH
A2
D(A2)
PRELIMINARY
DON’T CARE
D(A2 + 1)
t
WES
BURST WRITE
t
WEH
D(A2 + 1)
UNDEFINED
ADV suspends burst
D(A2 + 2)
X
LOW.
ADSC extends burst
D(A2 + 3)
t ADS
A3
D(A3)
t ADH
t ADVS
Extended BURST WRITE
t WES
D(A3 + 1)
t ADVH
t WEH
D(A3 + 2)
CY7C1361C
CY7C1363C
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