CY7C1363C CYPRESS [Cypress Semiconductor], CY7C1363C Datasheet - Page 7

• Manufacturer Part Number: CY7C1363C
• Description: 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05541 Rev. *A
Pin Definitions
A
BW
BW
GW
CLK
CE
CE
CE
OE
ADV
ADSP
ADSC
BWE
ZZ
DQ
DQP
MODE
V
V
V
0
DD
DDQ
SS
, A
1
2
3
s
A
C
[2]
,BW
,BW
X
1
Name
, A
B
D
I/O Power Supply Power supply for the I/O circuitry.
Asynchronous
Asynchronous
Power Supply
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Ground
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Clock
Static
I/O-
I/O-
I/O
Address Inputs used to select one of the address locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE
active. A
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written, regardless of the values on BW
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
HIGH. CE
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
a new external address is loaded.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
a new external address is loaded.
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE is masked during the first clock of a read cycle
when emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automat-
ically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A
asserted, only ADSP is recognized. ASDP is ignored when CE
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A
asserted, only ADSP is recognized.
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of
the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW,
the pins behave as outputs. When HIGH, DQ
condition. The outputs are automatically three-stated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ
During write sequences, DQP
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
or left floating selects interleaved burst sequence. This is a strap pin and should remain
static during device operation. Mode Pin has an internal pull-up.
Power supply inputs to the core of the device.
Ground for the core of the device.
[1:0]
1
PRELIMINARY
is sampled only when a new external address is loaded.
[1:0]
[1:0]
feed the 2-bit counter.
are also loaded into the burst counter. When ADSP and ADSC are both
are also loaded into the burst counter. When ADSP and ADSC are both
1
2
1
and CE
and CE
and CE
3
3
2
[2]
[2]
X
to select/ deselect the device.CE
is controlled by BW
to select/deselect the device. CE
to select/deselect the device. ADSP is ignored if CE
Description
s
and DQP
X
correspondingly.
X
1
, CE
are placed in a three-state
2
1
, and CE
3
is deasserted HIGH.
2
is sampled only when
is sampled only when
CY7C1361C
CY7C1363C
3
[2]
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are sampled
X
and BWE).
s
1
.
DD
is