CY7C1363C CYPRESS [Cypress Semiconductor], CY7C1363C Datasheet - Page 15

• Manufacturer Part Number: CY7C1363C
• Description: 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05541 Rev. *A
3.3V TAP AC Test Conditions
Input pulse levels ........ ........................................V
Input rise and fall times ...................... ..............................1ns
Input timing reference levels ...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
3.3V TAP AC Output Load Equivalent
TAP DC Electrical Characteristics And Operating Conditions
otherwise noted)
Identification Register Definitions
V
V
V
V
V
V
I
Revision Number (31:29)
Device Depth (28:24)
Device Width (23:18)
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Note:
11. All voltages referenced to V
12. Bit #24 is “1” in the Register Definitions for both 2.5v and 3.3v versions of this device.
Parameter
X
OH1
OH2
OL1
OL2
IH
IL
TDO
Instruction Field
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
[11]
Z = 50
O
[12]
Description
SS
(GND) .
1.5V
20pF
00000110100
50
CY7C1361C
(256K x36)
I
I
I
I
I
I
GND < V
000001
100110
OH
OH
OH
OL
OL
OL
01011
000
1
= 8.0 mA
= 8.0 mA
= 100 µA
= –4.0 mA
= –1.0 mA
= –100 µA
PRELIMINARY
SS
Description
to 3.3V
IN
< V
DDQ
00000110100
CY7C1363C
(512K x18)
000001
010110
01011
2.5V TAP AC Test Conditions
Input pulse levels
Input rise and fall time .....................................................1 ns
Input timing reference levels................... ......................1.25V
Output reference levels .................. ..............................1.25V
Test load termination supply voltage .................... ........1.25V
2.5V TAP AC Output Load Equivalent
000
1
TDO
Describes the version number.
Reserved for Internal Use
Defines memory type and architecture
Defines width and density
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
(0°C < TA < +70°C; V
V
V
V
V
V
V
V
V
V
V
V
V
Conditions
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
......................................... V
Z = 50
= 3.3V
= 2.5V
= 3.3V
= 2.5V
= 3.3V
= 2.5V
= 3.3V
= 2.5V
= 3.3V
= 2.5V
= 3.3V
= 2.5V
O
Description
DD
1.25V
Min.
–0.5
–0.3
2.4
2.0
2.9
2.1
2.0
1.7
= 3.3V ±0.165V unless
–5
CY7C1361C
CY7C1363C
20pF
50
V
V
DD
DD
Page 15 of 30
Max.
0.4
0.4
0.2
0.2
0.7
0.7
5
SS
+ 0.3
+ 0.3
to 2.5V
Unit
µA
V
V
V
V
V
V
V
V
V
V
V
V