CY7C1363C CYPRESS [Cypress Semiconductor], CY7C1363C Datasheet - Page 8

• Manufacturer Part Number: CY7C1363C
• Description: 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05541 Rev. *A
Pin Definitions
V
TDO
TDI
TMS
TCK
NC
V
SSQ
SS
/DNU
Name
(continued)
JTAG serial output
JTAG serial input
JTAG serial input
Synchronous
Synchronous
Synchronous
Ground/DNU
I/O Ground
JTAG-
Clock
I/O
–
Ground for the I/O circuitry.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
JTAG feature is not being utilized, this pin should be left unconnected. This pin is not
available on TQFP packages.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being utilized, this pin can be left floating or connected to V
up resistor. This pin is not available on TQFP packages.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being utilized, this pin can be disconnected or connected to V
is not available on TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to V
No Connects. Not internally connected to the die. 18M, 36M, 72M, 144M and 288M are
address expansion pins are not internally connected to the die.
This pin can be connected to Ground or should be left floating.
PRELIMINARY
SS
. This pin is not available on TQFP packages.
Description
CY7C1361C
CY7C1363C
DD
through a pull
Page 8 of 30
DD
. This pin