PCF8811U/2DA/1 NXP [NXP Semiconductors], PCF8811U/2DA/1 Datasheet - Page 26

• Manufacturer Part Number: PCF8811U/2DA/1
• Description: 80 x 128 pixels matrix LCD driver
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
10. Serial interfacing (SPI and serial interface)
PCF8811_4
Product data sheet
10.1.1 Write mode
10.1 Serial peripheral interface lines
Table 8.
The parallel interface timing diagram for the 6800 series is given in
Figure 39
connected to the enable (E) input. In
input (SCE) and the enable input (E) is tied HIGH.
Communication with the microcontroller can also occur via a clock-synchronized Serial
Peripheral Interface (SPI). It is possible to select between either a 3-line (SPI or serial
interface) or a 4-line serial peripheral interface. Selection is achieved via PS[2:0];
see
The serial peripheral interface is a 3-line or 4-line interface for communication between
the microcontroller and the LCD driver chip. The 3 lines are:
For the 4-line serial peripheral interface a separate D/C line is added.
The PCF8811 is connected to the serial data I/O (SDA) of the microcontroller by
connecting the two pads SDATA (data input) and SDO (data output) together.
The display data/command indication may be controlled either via software or the D/C
select pad. When the D/C pad is used, display data is transmitted when D/C is HIGH, and
command data is transmitted when D/C is LOW; see
D/C is not used, the display data length instruction is used to indicate that a specific
number of display data bytes (1 to 255) are to be transmitted; see
byte after the display data string is handled as an instruction command.
When the 3-line SPI interface is used, the display data/command is controlled by software.
If SCE is pulled HIGH during a serial display data stream, the interrupted byte is invalid
data but all previously transmitted data is valid. The next byte received will be handled as
an instruction command; see
D/C
0
0
1
1
•
•
•
SCE (chip enable)
SCLK (serial clock)
SDATA (serial data)
Section
and
6800 series parallel interface functions
7.1.12).
Figure
40. The timing diagrams differ because in
Rev. 04 — 27 June 2008
Figure
R/W/WR
0
1
0
1
18.
Figure 40
the clock is connected to the chip enable
Figure 15
80 x 128 pixels matrix LCD driver
Operation
command data write
read status register
display data write
none
and
Figure 39
Figure
Section
Figure
PCF8811
© NXP B.V. 2008. All rights reserved.
17. The next
the clock is
16. When pad
16.1,
26 of 81