PCF8811U/2DA/1 NXP [NXP Semiconductors], PCF8811U/2DA/1 Datasheet - Page 73

• Manufacturer Part Number: PCF8811U/2DA/1
• Description: 80 x 128 pixels matrix LCD driver
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 39.
[1]
[2]
PCF8811_4
Product data sheet
Step Pad
1
2
3
4
5
6
7
8
9
10
11
12
An alternative ending could be to stay in CALMM mode
13
X = value without meaning.
The data for the bits is not in the correct shift register position until all bits have been sent.
EXT
X
X
X
X
X
X
X
X
X
X
X
X
-
Sequence for filling the shift register; example 1
D/C R/W/WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
18.1.6 Example sequence for filling the shift register
18.1.7 Programming flow
0
0
0
0
0
0
0
0
0
0
0
0
-
0
0
0
0
0
0
0
0
0
0
0
0
-
An example of the sequence of commands and data is shown in
the shift register is filled with the following data: MMVOPCAL = 4 (1 1100b), MMTC = 2
(010b) and the seal bit is logic 0.
It is assumed that the PCF8811 has just been reset. After transmitting the last bit the
PCF8811 can either exit or remain in the CALMM mode; see
be noted that while in CALMM mode the interface does not recognize commands in the
normal sense.
After this sequence has been applied it is possible to observe the impact of the data
shifted in. The described sequence is, however, not useful for OTP programming because
the number of bits with the value logic 1 is greater than that allowed for programming;
see
Programming is achieved whilst in CALMM mode and with the application of the
programming voltages. As mentioned previously, the data for programming the OTP cell is
contained in the corresponding shift register cell. The shift register cell must be loaded
Fig 53. Shift register contents after example sequence; see
Section
Command byte
1
1
1
1
1
1
1
1
1
1
0
1
-
18.1.7. The shift register after this action is shown in
X
X
X
X
X
X
X
X
X
1
0
1
-
direction
shifting
X
X
X
X
X
X
X
X
X
1
0
1
-
Rev. 04 — 27 June 2008
BIT = 0
SEAL
X
X
X
X
X
X
X
X
X
0
0
1
-
OTP SHIFT REGISTER
X
X
X
X
X
X
X
X
X
0
0
1
-
LSB
0
[1]
MMTC[2:0]
X
X
X
X
X
X
X
X
X
0
0
1
-
1
0
1
X
X
X
X
X
X
X
X
X
1
-
MSB
0
1
0
1
1
1
0
0
0
1
0
0
0
LSB
-
0
Action
exit power-down
wait 5 ms for refresh to take effect
enter CALMM mode
shift in data; MMVOPCAL[4] is first bit
MMVOPCAL[3]
MMVOPCAL[2]
MMVOPCAL[1]
MMVOPCAL[0]
MMTC[2]
MMTC[1]
MMTC[0]
seal bit; exit CALMM mode
seal bit; remain in CALMM mode
80 x 128 pixels matrix LCD driver
0
MMVOPCAL[4:0]
Table 39
Table
1
Table
Figure
1
39, Step 1. It should
39. In this example
PCF8811
mgw765
© NXP B.V. 2008. All rights reserved.
MSB
53.
1
73 of 81
[2]