PCF8811U/2DA/1 NXP [NXP Semiconductors], PCF8811U/2DA/1 Datasheet - Page 34

• Manufacturer Part Number: PCF8811U/2DA/1
• Description: 80 x 128 pixels matrix LCD driver
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF8811_4
Product data sheet
Fig 30. Data transfer timing format in F/S-mode and Hs-mode
SDAH
SCLH
SDAH
SCLH
= Master current source pull-up
= Resistor pull-up
S
t
H
Sr
As no device is allowed to acknowledge the master code, the master code is followed by a
not-acknowledge (A). After this A bit, and the SCLH line pulled up to a HIGH level, the
active master switches to Hs-mode and enables at t
the SCLH signal; see
The active master will then send a repeated START condition (Sr) followed by a 7-bit slave
address (SLA) with a R/W bit, and receives an acknowledge bit (A) from the selected
slave.
After each acknowledge bit (A) or not-acknowledge bit (A) the active master disables its
current source pull-up circuit. The active master re-enables its current source again when
all devices have been released and the SCLH signal reaches a HIGH level. The rising of
the SCLH signal is done by a pull-up resistor and therefore is slower, the last part of the
SCLH rise time is speeded up because the current source is enabled. Data transfer only
switches back to F/S-mode after a STOP condition (P).
A write sequence after the Hs-mode is selected is shown in
initiated with a START condition (S) from the I
address. All slaves with the corresponding address acknowledge in parallel, the remainder
will ignore the I
1
1
2 to 5
7-bit SLA
2
C-bus transfer.
6
2 to 5
7
8-bit master code 0000 1xxx
Figure
Rev. 04 — 27 June 2008
R/W
8
9
30.
A
F/S-mode
Hs-mode
1
6
2 to 5
n + (8-bit data
2
7
C-bus master which is followed by the slave
6
7
H
the current-source pull-up circuit for
+
80 x 128 pixels matrix LCD driver
8
8
A/A)
9
Figure
A
9
Sr P
t
31. The sequence is
FS
t
1
If Sr (dotted lines)
then Hs-mode
If P then
F/S-mode
PCF8811
© NXP B.V. 2008. All rights reserved.
t
H
msc618
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