PCF8811U/2DA/1 NXP [NXP Semiconductors], PCF8811U/2DA/1 Datasheet - Page 65
PCF8811U/2DA/1
Manufacturer Part Number
PCF8811U/2DA/1
Description
80 x 128 pixels matrix LCD driver
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.PCF8811U2DA1.pdf
(81 pages)
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NXP Semiconductors
Table 35.
V
[1]
[2]
[3]
PCF8811_4
Product data sheet
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
C
V
V
SCLH
SU;STA
HD;STA
LOW
HIGH
SU;DAT
HD;DAT
rCL
rCL1
fCL
rDA
fDA
SU;STO
SP
DD1
nL
nH
b
All specified timings are based on 20 % and 80 % of V
For bus line loads C
A device must internally provide a data hold time to bridge the undefined part between V
signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
= 1.8 V to 3.3 V; V
I
2
Parameter
SCLH clock frequency
set-up time for a repeated
START condition
hold time (repeated) START
condition
LOW period of the SCLH
clock
HIGH period of the SCLH
clock
data set-up time
data hold time
rise time of SCLH signal
rise time of SCLH signal after
a repeated START condition
and after an acknowledge bit
fall time of SCLH signal
rise time of SDAH signal
fall time of SDAH signal
set-up time for STOP
condition
pulse width of spikes that
must be suppressed by the
input filter
capacitive load for each bus
line
noise margin at the LOW level for each connected device
noise margin at the HIGH
level
C-bus characteristics; Hs-mode
b
between 100 pF and 400 pF the timing parameters must be linearly interpolated.
SS
= 0 V; V
LCD
9 V; T
Conditions
SDAH and SCLH
SDAH and SCLH lines
SDAH + SDA line and
SCLH + SCL line
(including hysteresis)
for each connected device
(including hysteresis)
amb
= 40 C to +85 C; unless otherwise specified
Rev. 04 — 27 June 2008
DD
.
[2]
0.1V
0.2V
C
b
20
Min
160
160
160
160
= 100 pF (max)
60
10
10
10
10
10
10
0
0
0
0
DD1
DD2
IH
[3]
80 x 128 pixels matrix LCD driver
and V
IL
Max
100
400
3.4
of the falling edge of the SCLH
70
40
80
40
80
80
5
-
-
-
-
-
-
-
-
[1]
; see
0.1V
0.2V
C
20
Min
160
160
320
120
160
b
10
20
20
20
20
20
0
0
-
-
PCF8811
[3]
© NXP B.V. 2008. All rights reserved.
= 400 pF
DD1
DD2
Figure
Max
150
160
160
160
400
400
1.7
80
80
46.
5
-
-
-
-
-
-
-
-
[2]
65 of 81
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
V
V
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